High Productivity, Robust FPGA Programming Tool

Award Information
Agency:
Department of Defense
Branch
Navy
Amount:
$749,901.00
Award Year:
2012
Program:
SBIR
Phase:
Phase II
Contract:
N68936-12-C-0191
Award Id:
n/a
Agency Tracking Number:
N111-014-0557
Solicitation Year:
2011
Solicitation Topic Code:
N111-014
Solicitation Number:
2011.1
Small Business Information
20271 Goldenrod Lane, Suite 2008, Germantown, MD, -
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
008171329
Principal Investigator:
Michael Babst
President
(301) 977-5970
mspb@dsplogic.com
Business Contact:
Michael Babst
President
(301) 977-5970
mspb@dsplogic.com
Research Institute:
Stub




Abstract
Field Programmable Gate Arrays (FPGAs) are a very attractive, and often necessary, computational resource for many Digital Signal Processing (DSP) applications. Their balance of performance, power consumption, and size make them ideally suited to SWAP-constrained sensor, communication, and guidance applications. However, the lengthy FPGA development and validation cycle, with limited application portability, and limited design re-use contribute to relatively high life-cycle costs compared to modern embedded software systems. A faster and more robust method to program advanced Digital Signal Processing (DSP) algorithms on Field Programmable Gate Arrays (FPGAs) is required. We propose the development of an Electronic System Level (ESL) tool targeted specifically toward programming DSP algorithms on FPGAs. Algorithms are described by algorithm experts at a high-level using a highly-expressive model of computation. The model of computation also supports robust FPGA code generation and verification capability to eliminate the error-prone phases of low-level design specification and manual hardware programming by dedicated hardware engineers.

* information listed above is at the time of submission.

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