Design Tools For Tela Canvas Highly Regular Circuit Geometries

Award Information
Agency:
Department of Defense
Branch
Defense Advanced Research Projects Agency
Amount:
$1,499,100.00
Award Year:
2012
Program:
SBIR
Phase:
Phase II
Contract:
HR0011-11-9-0007
Award Id:
n/a
Agency Tracking Number:
10SB2-0210
Solicitation Year:
2010
Solicitation Topic Code:
SB102-003
Solicitation Number:
2010.2
Small Business Information
485 Alberto Way, Suite 115, Los Gatos, CA, -
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
789563785
Principal Investigator:
MichaelSmayling
Sr. VP of Technology
(408) 558-6321
mike@tela-inc.com
Business Contact:
PeterCalverley
CFO
(408) 558-6325
peterc@tela-inc.com
Research Institute:
Stub




Abstract
Through this DARPA SBIR Phase II program, we plan to extend our previous point-solution demonstration (DARPA seedlings) to include logic, SRAM, and IO's and deliver the EDA tool to enable DoD ASICs to take full advantage of our commercial experience. Our Phase I effort to date has shown a path to the EDA tools and design infrastructure needed to meet the goals outlined above. The software engineering tool"Gridded Design Assistant"has been demonstrated for a representative set of ten standard cells. We are well along in the second part of the Phase I effort, i.e. demonstrating an SRAM bit-cell and peripheral circuitry compatible with the regular layout style used for the standard cells.

* information listed above is at the time of submission.

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