Field Programmable Gate Array (FPGA) Physical Unclonable Functions

Award Information
Agency:
Department of Defense
Branch
n/a
Amount:
$723,978.00
Award Year:
2012
Program:
SBIR
Phase:
Phase II
Contract:
W31P4Q-12-C-0133
Award Id:
n/a
Agency Tracking Number:
O2-1194
Solicitation Year:
2010
Solicitation Topic Code:
OSD10-A02
Solicitation Number:
2010.2
Small Business Information
110 Johnston Street, SE, Decatur, AL, -
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
Y
Duns:
794777847
Principal Investigator:
JamesLewis
Principle Engineer
(256) 905-0775
james.lewis@lewisinnovative.com
Business Contact:
TerriWomack
Contracting
(256) 905-0775
terri.womack@lewisinnovative.com
Research Institute:
Stub




Abstract
LIT accomplished all Phase I goals and technical objectives. In Phase I LIT produced an effective Random Number Generator (RNG) and tested two PUF designs. The PUF designs showed greatly improved Entropy and Stability over other technologies. LIT"s Entropy Goal for Phase II is 100% (already proven by analysis) and the Stability goal is one bit error per million bits. In Phase II LIT will mature this PUF technology by producing 3 programmable logic IP Blocks: Asymmetric PUF (APUF), Memory Authentication Parameter Sensor (LIT"s memory incorporating PUF), and a Random Number Generator. LIT partner Lockheed Martin Mission Systems and Signals will test the IP Blocks (Cores) in tactical hardware to achieve TRL 8. LIT will produce interface software to use with the PUF cores allowing a customer to access, test, evaluate, and characterize the PUF performance in their application. LIT is producing a PUF test suite to accumulate and process test results in order to quantify Variation, Entropy, and Stability metrics. At the end of Phase II LIT will provide two licenses for each PUF core and provide 2 day training on the use of the IP Blocks and related tools.

* information listed above is at the time of submission.

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