FleX-3D Wafer Processing for Chip Stacking and Interconnect

Award Information
Agency:
Department of Energy
Branch
n/a
Amount:
$149,977.00
Award Year:
2013
Program:
SBIR
Phase:
Phase I
Contract:
DE-FG02-13ER90532
Award Id:
n/a
Agency Tracking Number:
84318
Solicitation Year:
2013
Solicitation Topic Code:
40 e
Solicitation Number:
DE-FOA-0000760
Small Business Information
3100 S Vista Ave Ste 230, Boise, ID, 83705-7368
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
076338677
Principal Investigator:
DaleWilson
Mr.
(208) 336-2773
dalewilson@americansemi.com
Business Contact:
LorelliHackler
Mrs.
() -
lhackler@americansemi.com
Research Institute:
Stub




Abstract
Reliable, readily-manufacturable technologies are needed to create the next generation of high-density, high-functionality 3D integrated circuits (ICs) for integrating silicon pixel detectors with CMOS read-out ICs. Current methods for 3D IC development are severely limited by the thickness of the CMOS wafers and the restrictions that result due to the diameter of the through-silicon vias (TSVs) that connect the chips together. The thinner these CMOS wafers can be made, the smaller the TSV diameter and the more efficient the TSVs become which will in-turn improve the performance of the silicon pixel detectors and other products that are enhanced by 3D integration. American Semiconductor proposes modifying its existing FleX process to support 3D integration of CMOS ICs and silicon pixel detectors. American Semiconductor has demonstrated the revolutionary FleX process for creating flexible, ultra-thin, single- crystalline CMOS with multi-layer metal interconnect. FleX is a post-fab process that can be applied to any SOI CMOS wafer and delivers fully functional, flexible wafers with a final silicon thickness of & lt;200nm. In Phase I, American Semiconductors FleX process will be enhanced to demonstrate 3D chip stacking including manufacture of the TSVs and will immediately demonstrate feasibility for deep sub- micron TSVs. In Phase II, the TSVs will be optimized, metal interconnect layers will be added, and multiple chip stacks will be demonstrated. Successful demonstration and commercialization of FleX 3D ICs will benefit DoE by supporting creation of future generations of silicon pixel detectors for use in nuclear and high-energy physics. In the commercial markets, improved 3D chip stacking methods will provide benefits to high-performance computing, cell phones, and CMOS imagers. Current methods for 3D IC development are limited by the thickness of the CMOS wafers and the resulting dimensions of the TSVs that connect the layers together. The thinner these CMOS wafers can be made, the smaller and more efficient the through-silicon vias become which will in-turn improve the performance of silicon pixel detectors for DoE and commercial applications. In Phase I, American Semiconductors FleX process for creating flexible, ultra-thin ( & lt;200nm), single-crystalline CMOS will be enhanced to demonstrate 3D chip stacking including manufacture of through-silicon vias (TSVs). In Phase II, the TSVs will be optimized, metal interconnect will be added, and multiple chip stacks will be demonstrated. Commercial Applications and Other Benefits: The FleX 3D chip stacking process is applicable to numerous commercial applications including 3D integration of high performance logic with high density memory. The technology provides the opportunity to integrate technologies based on different materials such as III-V and silicon while maintaining the capability to fabricated sophisticated layers post bonding.

* information listed above is at the time of submission.

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