Low-power Cross-Correlator ASIC

Award Information
Agency:
National Aeronautics and Space Administration
Branch
n/a
Amount:
$950,000.00
Award Year:
2013
Program:
SBIR
Phase:
Phase II
Contract:
NNX13CP01C
Award Id:
n/a
Agency Tracking Number:
115685
Solicitation Year:
2011
Solicitation Topic Code:
S1.03
Solicitation Number:
n/a
Small Business Information
CA, Culver City, CA, 90230-4650
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
831566877
Principal Investigator:
Denis Zelenin
Principal Investigator
(310) 683-2628
denis@pacificmicrochip.com
Business Contact:
Dalius Baranauskas
Business Official
(310) 683-2628
dalius@pacificmicrochip.com
Research Institution:
Stub




Abstract
The NASA's PATH mission includes the GeoSTAR satellite that carries aboard a microwave sounder employing an array of 375 microwave antennas with corresponding receivers. Each receiver is tuned to the 180GHz frequency, while the intermediate frequency (IF) reaches 500MHz. The IF signal is quantized at 1GHz with 2-bit accuracy. The resulting data rate is 700Gb/s. This data has to be pre-processed aboard the satellite before it can be transmitted to Earth for further processing. One of the steps of such data processing is cross-correlation. For a space borne instrument, power dissipation and radiation hardness are among the most important requirements. Pacific Microchip Corp. is designing an ASIC that includes a cross-correlation unit with interfaces for the GeoSTAR's receivers. The ASIC will have greatly reduced power consumption compared to that of the FPGA-based or classic ASIC-based implementations. This ASIC must be designed and integrated with already existing system components of the GeoSTAR instrument. The ASIC includes cross-correlation cells based on novel architecture. The deep submicron SOI CMOS technology selected for the ASIC's fabrication will increase its tolerance to the total ionizing dose (TID) and reduce the probability of radiation-induced latch-up. The design of the ASIC will follow design for testability (DFT) methods, which will simplify characterization and testing of the fabricated ASIC, reduce risk and lower the cost of the product.

* information listed above is at the time of submission.

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