A High Performance 90nm"Schottky"CMOS Process for Mitigation of Parasitic Bipolar Effects and Dramatically Reduced Bit Upset Rates

Award Information
Agency:
Department of Defense
Branch
n/a
Amount:
$750,000.00
Award Year:
2013
Program:
SBIR
Phase:
Phase II
Contract:
FA9453-13-C-0011
Award Id:
n/a
Agency Tracking Number:
F103-087-2138
Solicitation Year:
2010
Solicitation Topic Code:
AF103-087
Solicitation Number:
2010.3
Small Business Information
112 Ellsworth Pl, Chapel Hill, NC, -
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
962597527
Principal Investigator:
John Snyder
Chief Technical Officer
(619) 590-0605
john.p.snyder@gmail.com
Business Contact:
Darin Davis
President
(919) 539-8821
darind@mindspring.com
Research Institution:
Stub




Abstract
ABSTRACT: Avolare2 proposes to establish a 90nm metal source/drain"Schottky"CMOS process at Cypress Semiconductor"s high volume manufacturing facility in Bloomington, MN. Schottky CMOS will have a profound impact on the performance and reliability of most of the integrated circuits (ICs) providing critical functionality for electronic systems operating in high radiation environments. The Schottky process flow will be based on an existing conventional 90nm process already in production at Cypress. Development of high-performance digital and mixed-signal components by the design community will allow for greater levels of machine-intelligence in spacecraft, aircraft, and missile applications. Schottky CMOS is 100% compatible with current CMOS process equipment and requires fewer process steps, providing military IC suppliers with a convenient path to upgrade existing fabrication lines and offer ICs with latch-up and single event upset (SEU) immunity at faster speeds and lower power consumption. The Schottky transistor"s performance and SEU immunity benefits are expected to become even more pronounced at advanced linewidths (45nm and below), ushering in a new era of component innovation for military and commercial systems alike, accelerating adoption by commercial IC foundries and enabling the development of novel computing, communication, and consumer electronic products. BENEFIT: Space-based systems and avionics applications require highly integrated, cost-effective, state-of-the-art integrated circuits (ICs) capable of withstanding harsh radiation laden environments. Scaling conventional semiconductor transistors from 2000 nm to 150 nm provides the IC with speed-power-cost benefits, but the traditional transistor becomes more susceptible to radiation effects at smaller geometries. The successful development of rad-hard, metal source/drain Schottky-barrier CMOS (SB-CMOS) technology will enable military IC suppliers to take advantage of the performance benefits of advanced circuit geometries (90 nm and below) without sacrificing reliability due to radiation effects, providing defense and aerospace system contractors access to the critical high-performance components with minimum power, size, weight, and cost.

* information listed above is at the time of submission.

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