Radiation-Hardened, Deep-Submicron Application Specific Integrated Circuit

Award Information
Department of Defense
Solitcitation Year:
Solicitation Number:
Air Force
Award Year:
Phase II
Agency Tracking Number:
Solicitation Topic Code:
Small Business Information
Silicon Space Technology Corporation
5918 West Courtyard Drive, Suite 330, Austin, TX, -
Hubzone Owned:
Woman Owned:
Socially and Economically Disadvantaged:
Principal Investigator
 JW Smith
 (650) 968-1056
Business Contact
 Jon Gwin
Title: Vice President
Phone: (512) 347-1814
Email: jgwin@siliconspacetech.com
Research Institution
ABSTRACT: This proposal"s objective is for Silicon Space Technology (SST) to develop a high-performance radiation-hardened design platform for building radiation-hardened Application Specific Integrated Circuits (ASICs) with a gate count>10M and Total Ionizing Dose (TID) performance>1 Mrad. Meeting this objective enables building of satellites that can meet aggressive, leading-edge size, weight, and power (SWAP) goals. SST"s proprietary HardSIL & #61652; technology has been successfully integrated within 250nm, 180nm and 130nm processes from multiple manufacturers resulting in hardened processes>1 Mrad TID. Requirements for an ASIC platform were developed through meetings with system prime contractors and Mil/Aero customers combined with a survey of existing radiation-hardened products. A structured ASIC platform with metal-programmable cells and IOs will be developed using a 130nm process enhanced with HardSIL & #61652; technology to provide a metal-programmable system on a chip (MPSoC) capability. Results from modeling the MPSoC platform based upon a 130nm HardSIL & #61652; enhanced process with commercial EDA synthesis and layout tools from Cadence showed a usable gate density of 90K gates/mm2. Therefore a 10x10mm2 interior chip area would have 12M raw gates and 9M usable gates with TID performance>1Mrad. BENEFIT: Silicon Space believes the existing or potential military requirements and military potential for the results of this proposed Phase II 130nm SOC program were touched upon within the Phase I solicitation. Excerpts state"The enduring role of semiconductors in satellite communications will continue to fuel advances in platform capabilities for the foreseeable future. Digital processing will have to operate at significantly higher data rates and consume less power per gate to meet the ever increasing demands of battlefield communications, and this objective requires a continuous push downward on the energy/operation of semiconductors, which requires attention to the optimization of the associated processes."It also stated that military space systems need much higher performance circuits than are currently available through captive rad-hard foundries. Availability of the 130nm low-power RH MPSoC cell library will allow higher performance systems in space. Our 130nm low-power RH metal programmable system-on-a-chip cell library addresses the latch-up, total ionizing dose, and single-event effects requirements including the"tolerance to even higher radiation levels"aspect. These performance capabilities also result in improved reliability for long-term missions. SST believes AFRL, SMC and MDA are the primary DoD agencies most likely to benefit from this project. All three have expressed interest in related-work programs, so we believe there may be interest by at least one in a federally-funded CPP and/or Phase III effort.

* information listed above is at the time of submission.

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