Advanced Chip Integration for Enhanced Arrays

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA8651-13-M-0173
Agency Tracking Number: F131-098-0079
Amount: $149,757.00
Phase: Phase I
Program: SBIR
Awards Year: 2013
Solicitation Year: 2013
Solicitation Topic Code: AF131-098
Solicitation Number: 2013.1
Small Business Information
1400 E. Angela Blvd, Unit 107, South Bend, IN, -
DUNS: 831862227
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Jason Kulick
 President
 (574) 217-4612
 jason.kulick@indianaic.com
Business Contact
 Jason Kulick
Title: President
Phone: (574) 217-4612
Email: jason.kulick@indianaic.com
Research Institution
N/A
Abstract
ABSTRACT: Improvements such as increased array size and better non-uniformity correction have been made to resistive emitter arrays fabricated on silicon (Si). There exist additonal wavelengths of interest whose emitter devices require fabrication in other materials, such as gallium arsenide (GaAs). For both Si and GaAs substrate materials, attempts to"tile"small arrays into larger ones for reasons of cost and design flexibility have met with limited success. Issues such as chip-to-chip I/O pitch, relatively large"seams"created by gaps between adjacent chips, and precision chip alignment all have posed significant problems to tiling smaller chips into larger arrays. Integrating drive and control electronics further complicates this problem. The new electronic packaging technology developed by Indiana Integrated Circuits, LLC and known as"Quilt Packaging"(QP) can alleviate many of the problems associated with tiling arrays, while delivering desired electronic performance, thermal management and design flexibility. QP enables sub-micron chip-to-chip alignment, customizable chip I/O potentially as dense as 10 micron pitch, and can reduce"seams"between array elements to less than 10 microns. The IIC team proposes to integrate QP technology for application to scalable, flexible, lower-cost GaAs-based emitter arrays for a new generation of high-performance infrared scene projector systems. BENEFIT: There is considerable interest from the scene simulation community in the production of large scale IRSP systems for testing large format imagers. Near term commercialization would be the production of IRSP systems based on the gallium arsenide (GaAs) Quilt Packaging processes proposed for this SBIR effort, or their modification to address similar IRSP technologies. If arrays can be tiled on all 4 sides, then emitter arrays will no longer be limited by RIIC size/yield, drastically reducing array cost. Effectively any size array could be fabricated by joining the requisite number of tiles, though power, thermal and carrier size limitations will limit the practical size of a tiled array. Another potential application would apply to large arrays for infrared imaging, and the proposed technology could also be applied to other types of focal plane arrays. In addition to the military/defense market for IR detection arrays, there are significant commercial applications if the cost curve can be bent down enough. Bio-medical, security scanning, standoff detection and manufacturing quality control are all potential markets for low-cost, large-format imaging arrays. It is anticipated that in addition to these known markets, new markets will emerge for IR imagers as the system costs decrease.

* Information listed above is at the time of submission. *

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