Rise Tool for Updating Legacy Code to Multi-thread, Multi-core Processor Systems

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N68335-13-C-0421
Agency Tracking Number: N132-099-0346
Amount: $79,972.00
Phase: Phase I
Program: SBIR
Awards Year: 2013
Solicitation Year: 2013
Solicitation Topic Code: N132-099
Solicitation Number: 2013.2
Small Business Information
Harmonia Holdings Group
2020 Kraft Drive, Suite 1000, Blacksburg, VA, -
DUNS: 556397615
HUBZone Owned: Y
Woman Owned: Y
Socially and Economically Disadvantaged: Y
Principal Investigator
 Marc Abrams
 PI
 (540) 951-5901
 mabrams@harmonia.com
Business Contact
 Pallabi Saboo
Title: CEO
Phone: (540) 951-5915
Email: psaboo@harmonia.com
Research Institution
N/A
Abstract
Central Processing Unit (CPU) chip makers made two advancements in recent years: (1) hyper-threading (e.g., Intel HT technology) to allow a single processor core to execute multiple instructions simultaneously, and (2) fabrication of dies with multiple processor cores. Exploiting those requires new code in C#, Java, or other languages that embrace threads. A thread is a conventional sequential program, but threads can be scheduled to execute in parallel. A key challenge is that two threads must serialize their work on shared memory areas or data structures (or else one could destroy the data of the other thread), requiring special synchronization primitives (e.g., monitors, message passing). This is a non-trivial job for a programming team. Rise Multi-Core fills the need is for automated analysis that can improve older sequential code to make use of multiple cores. The Desired Future State is a tool to analyze existing legacy code and apply transformations it to effectively use threading and multi-cores to improve performance (e.g., lower time for route planning, or increased throughput for graphical operations).

* information listed above is at the time of submission.

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