Object-Accelerated Computational Fabric
Department of Defense
Defense Advanced Research Projects Agency
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3680 Boulder Hwy., Las Vegas, NV, 89121
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AbstractCPU technology has progressed to a point of diminishing marginal returns in its current direction. The great success of the highly pipelined sequential processor has now become a hindrance to the efficient scalability for the evolutionary escape route of cookie-cutter chip multi-processor (CMP) designs. RISC instruction sets exist because they are easy to decode and pipeline, but they have relatively low information density and operate on similarly primitive data types. If we look at the codes these CPUs are running, they are largely object-oriented languages. The lesson learned in the software world is that programmer productivity is relatively constant number of lines of code per day, whether assembly language or a much higher-level of abstraction in a modern object-based language. The information density and expressivity of the object-oriented language is much greater, as is the computational effort induced by each object method invocation. This is a good thing and should be emulated by hardware designers. We propose a package of several novel hardware-assisted object-based techniques to increase the value of our limited processor-to-network interfaces and the generally useful scalability of future CMP designs.
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