High Voltage High Frequency SiC Switch

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N00014-10-C-0104
Agency Tracking Number: N073-197-0610
Amount: $749,979.00
Phase: Phase II
Program: SBIR
Awards Year: 2010
Solicitation Year: 2007
Solicitation Topic Code: N07-197
Solicitation Number: 2007.3
Small Business Information
GeneSiC Semiconductor Inc.
43670 Trade Center Place, Suite 155, Dulles, VA, -
DUNS: 148969137
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: Y
Principal Investigator
 Ranbir Singh
 (703) 996-8200
Business Contact
 Ranbir Singh
Title: President
Phone: (703) 996-8200
Email: ranbir.singh@genesicsemi.com
Research Institution
The stringent power quality, size weight and volume requirements for operating next-generation intelligent power systems (NGIPS) require the development of revolutionary new semiconductor switch technology. The challenging specifications (>20 kHz, >10 kV) demanded by these applications are enabled by fully exploiting the superior electrical and thermal properties of the emerging power semiconductor material of choice: Silicon Carbide. In the Phase I, an innovative SiC device invented recently – the SuperJFET, was found to offer the best solution. Extensive analytical and 2D device simulations were conducted to accurately model SiC SuperJFET devices and its performance was verified. Test structures were fabricated to demonstrate critical fabrication steps that enable the realization of high performance SiC devices. Power modules were designed and fabricated that allows reliable packaging and testing of SiC devices. In this Phase II SBIR program, four batches of SiC SuperJFET devices will be designed and fabricated with successively increasing power levels to meet the program objectives. A high volume Silicon Carbide foundry will allow economical production of SuperJFET devices for successful commercialization with DoD prime contractors with high power conditioning systems expertise. A comprehensive military standards test plan will be implemented to enable a successful insertion into SSPS hardware.

* information listed above is at the time of submission.

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