Design and Fabrication Techniques for 3-Dimensional Integrated Circuits
Department of Defense
Defense Advanced Research Projects Agency
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5821 Sky Park Dr., Plano, TX, -
Socially and Economically Disadvantaged:
AbstractThe 3-D integration of systems through monolithic wafer stacking is an emerging technology that can alleviate power, delay, and area problems for digital circuits and can enable a host of new applications in the system on a chip design space. Currently, CAD tools for 3-D integration are severely lacking stagnating potentially explosive growth of the technology. GoofyFoot Labs proposes TESI3d, a CAD tool to efficiently and accurately explore the complex 3-D design space. We will develop a full-scale prototype, which will then be used to design and evaluate 3-D systems.
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