Innovative Approaches to Low Power, Sub-Threshold Electronic Circuits

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: W91CRB-10-C-0106
Agency Tracking Number: 08SB2-0729
Amount: $750,000.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: SB082-045
Solicitation Number: 2008.2
Solicitation Year: 2008
Award Year: 2010
Award Start Date (Proposal Award Date): 2010-06-21
Award End Date (Contract End Date): 2011-06-20
Small Business Information
1 Research Boulevard, Suite 200, Suite 200, Starkville, MS, -
DUNS: 791134542
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 George Ansel
 Senior Technical Staff
 (662) 320-1015
Business Contact
 James Merchant
Title: VPof Adv. Microelectronic
Phone: (662) 320-1018
Research Institution
This program proposes to demonstrate an ultra-low power design methodology and circuits for digital logic employing advanced dynamic voltage scaling (DVS) for asynchronous NULL Convention Logic (NCL) circuits operating in sub-threshold to super-threshold voltage regimes. The power supply voltages of logic block partitions will be independently set by on-chip voltage controllers based on the data processing rate requirements for each block. The proposed development includes design of sub-threshold to super-threshold level converter circuits, DVS control block, DC-DC converter, and supporting design infrastructure to implement digital logic System on Chip (SoC) designs targeted at infrared (IR) camera electronics.

* Information listed above is at the time of submission. *

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