SBIR Phase I: Low cost, scalable and selective electrochemical TSV fill technology for 3D IC interconnects

Award Information
Agency: National Science Foundation
Branch: N/A
Contract: 1315056
Agency Tracking Number: 1315056
Amount: $150,000.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: NM
Solicitation Number: N/A
Solicitation Year: 2012
Award Year: 2013
Award Start Date (Proposal Award Date): 2013-07-01
Award End Date (Contract End Date): 2014-06-30
Small Business Information
5388 NW Lianna Way, Portland, OR, 97229-8970
DUNS: 022592557
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Val Dubin
 (971) 327-4055
Business Contact
 Val Dubin
Phone: (971) 327-4055
Research Institution
This Small Business Innovation Research Phase I project advances a novel method to fabricate 3D IC interconnects. Physical and economical limitations for 2D scaling (Moore's Law) prevents further increase of integration density to improve the performance of integrated circuits (IC). These challenges have stimulated the development of 3D through-silicon via (TSV) technology (so called 'More than Moore') in order to increase the speed and the bandwidth of the devices as well as to decrease the form factor and power consumption of integrated microsystems. However, the implementation of 3D TSV technology is limited by the high cost of 3D TSV fill (due to the use of expensive vapor deposition and chemical-mechanical processes) and its poor scalability (due to low conformality of physical and chemical vapor deposited films) to high TSV aspect ratios and smaller via sizes (to increase I/O). The objective of this investigation is to address this problem in order to enable cost-effective and reliable fill of high aspect ratio 3D TSVs. This goal will be achieved with the use of novel electrochemical materials and processes enabling conformal anodic isolation and electroless barrier/seed films, as well as selective electrochemical Cu TSV filling. The broader impact/commercial potential of this project will be to accelerate the mass-scale adoption of low cost and scalable TSV technology in semiconductor manufacturing. The development of 3D TSV packaging is carried out by various companies in USA, Europe, Japan, Korea, Taiwan, etc. However, the high cost and low scalability 3D TSV filling process prevents mass-adoption of 3D IC interconnects. Our proprietary low-cost, scalable and selective (electrochemical TSV fill technology will allow us to decrease the cost of TSV fill technology by a factor of>2 and to increase the scalability by a factor of>3 to fabricate low cost, high speed, large bandwidth and broader functionality 3D devices. Therefore, the successful completion of this project would not only have a significant societal impact by accelerating 3D IC wafer technology adoption into state-of-art high performance digital devices such as next generation of smart phones, but also have positive economic impact by creating US semiconductor jobs and maintaining US technology leadership over a wide range of semiconductor applications.

* Information listed above is at the time of submission. *

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