SBIR Phase I: Multi-Core Sleep Convention Logic Processor

Award Information
Agency: National Science Foundation
Branch: N/A
Contract: 1315437
Agency Tracking Number: 1315437
Amount: $150,000.00
Phase: Phase I
Program: SBIR
Awards Year: 2013
Solicitation Year: 2012
Solicitation Topic Code: EI
Solicitation Number: N/A
Small Business Information
535 W. Research Center Blvd, Suite 135, M/S 2500, Fayetteville, AR, 72701-6948
DUNS: 968358452
HUBZone Owned: Y
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Jerry Frenkil
 (479) 571-2592
Business Contact
 Jerry Frenkil
Phone: (479) 571-2592
Research Institution
This Small Business Innovation Research (SBIR) Phase I project addresses the challenge of designing ultra-low power circuits using new asynchronous design techniques to dramatically reduce both dynamic power and leakage power. The objectives of this project are to demonstrate improved power characteristics on an industrial multi-core processor using Sleep Convention Logic (SCL), a type of asynchronous logic that automatically puts circuits to sleep to reduce leakage power. A 16 core processor will be implemented using SCL and compared to a synchronous implementation, both in the same 65nm technology. Both implementations will be based upon the same source design described in an industry standard Hardware Description Language (HDL) and the resulting SCL implementation will be compared against the synchronous implementation to demonstrate functional equivalency. Both the SCL and synchronous implementations will be characterized for dynamic and leakage power consumption, area, and timing. It is anticipated that the SCL implementation will be somewhat larger in area and have somewhat slower timing, but have significantly reduced dynamic and leakage power. The characterization effort will quantify these comparisons. This project is significant in that this will be the first comparison of SCL and synchronous implementations of an industrial circuit in a nanometer fabrication process. The broader impact/commercial potential of this project will be to establish asynchronous design methodologies based upon industry standards and to empirically quantify the benefits of using SCL for ultra-low power circuits and power sensitive applications. It is expected that SCL is especially well suited to system on chip (SoC) designs that employ a multitude of identical cores. Today, the number of cores used on SoCs is typically limited by total power consumption; if the power consumption of each core can be reduced dramatically, then the number of cores that can be placed on an SoC can be dramatically increased. Larger numbers of cores result in increased bandwidth and energy efficiency, thus enabling increased functionality especially in applications relying upon advanced signal processing such as high-speed wireless communications, remote sensing, embedded vision, and implantable medical devices. Hearing aids are but one example of applications requiring large amounts of signal processing at extremely low levels of power consumption. Today, limited battery life is a major issue inhibiting both market acceptance and personal convenience of advanced hearing aids. Results of this project will provide a path to easing such limitations thereby opening up new opportunities in personal communication and medical markets, among many others.

* Information listed above is at the time of submission. *

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