THE DEVELOPMENT OF EXTREMELY FAST RISC-BASED ALUS FOR CHARACTER STRING PROCESSING

Award Information
Agency:
National Aeronautics and Space Administration
Branch:
N/A
Amount:
$430,000.00
Award Year:
1988
Program:
SBIR
Phase:
Phase II
Contract:
N/A
Agency Tracking Number:
5110
Solicitation Year:
N/A
Solicitation Topic Code:
N/A
Solicitation Number:
N/A
Small Business Information
Accelerated Processors Inc.
2685 Marine Way, #1401, Mountain View, CA, 94043
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
N/A
Principal Investigator
 () -
Business Contact
 HAL NISSLEY
Title: INVESTIGATOR
Phone: () -
Research Institution
N/A
Abstract
GENERAL PURPOSE PROCESSOR ARITHMETIC LOGIC UNITS (ALUS) TYPICALLY IMPLEMENT LARGE MICRO-CODED INSTRUCTION SETS TO PROVIDE SYSTEM FLEXIBILITY, WITH THE ULTIMATE GOAL OF SUPPORTING A WIDE BASE OF APPLICATIONS. THE LARGE NUMBER OF INSTRUCTIONS RESULTS IN A COMPLEX, RELATIVELY SLOW CHIP ARCHITECTURE. IN EFFECT, BY BASING THEIR SYSTEMS ON GENERAL PURPOSE ALUS, COMPUTER MANUFACTURERS TRADE-OFF SPEED OF OPERATIONS IN FAVOR OF FLEXIBILITY. HOWEVER, HERE EXIST MANY APPLICATIONS FOR WHICH FLEXIBILITY IS NOT REQUIRED, BUT FOR WHICH SPEED IS THE MAIN GOAL. RISC-BASED SYSTEMS AIM FOR THIS MARKET NICHE. THIS PROPOSAL ADDRESSES THE DEVELOPMENT OF ASP, THE ACCELERATED STRING PROCESSOR. ASP UTILIZES A REDUCED INSTRUCTION SET COMPUTER (RISC) ARCHITECTURE TO PROVIDE PROCESSING OF CHARACTER STRINGS AT RATES IN EXCESS OF 2,000 MCOPS (MILLION CHARACTER OPERATIONS PER SECOND).

* information listed above is at the time of submission.

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