Reconfigurable Processors for Software Protection

Award Information
Agency:
Department of Defense
Amount:
$749,970.00
Program:
SBIR
Contract:
FA8650-04-C-8006
Solitcitation Year:
2003
Solicitation Number:
2003.2
Branch:
Air Force
Award Year:
2004
Phase:
Phase II
Agency Tracking Number:
O031-0154
Solicitation Topic Code:
OSD03-003
Small Business Information
ACCORD SOLUTIONS, INC.
3533 Albatross Street, San Diego, CA, 92103
Hubzone Owned:
N
Woman Owned:
Y
Socially and Economically Disadvantaged:
N
Duns:
836003459
Principal Investigator
 Carl Murphy
 Vice President and CTO
 (619) 692-9476
 carl.murphy@accordsol.com
Business Contact
 C. Murphy
Title: President and Contracts M
Phone: (619) 692-9476
Email: cmm@accordsol.com
Research Institution
N/A
Abstract
Based on the hidden, unique opcode invention made and demonstrated in Phase I and its integration with CyberDog Communications Inc Object Level Firewall(OLF) authentication, key management and encryption technology, Accord Solutions Inc proposes to prototype the Reconfigurable Architecture for Software Protection (RASP) System. The RASP System provides an extremely strong level of cryptographic protection from quantum and supercomputer brute force attacks, preventing compromise of high value HPC binary executables through reverse engineering. In addition, there is low impact on HPC software development, with minimal impact on typical HPC working sets, with slight latency increases for disk IO and interprocessor communication. The RASP system uniquely distributes a single binary executable to each processor authenticated to execute it. Authentication by the OLF provides assurance that access is made only by validated processors. Data input and output is likewise protected, but with different keys, ensuring that no user can access the binary executable for reverse engineering exploitation. Parallel processing uses a different set of RASP keys to protect interprocessor communication. The Phase II effort produces three prototypes: purely software, FPGA accelerated software and a printed circuit board. Each of these prototypes will be demonstrated (single, parallel and staged) using an instrumented test bed.

* information listed above is at the time of submission.

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