NOC - Network-on-a-Chip for Hardware-based Accelerated Simulation of Ad Hoc Mobile Communications Networks

Award Information
Agency:
Department of Defense
Branch
Army
Amount:
$99,998.00
Award Year:
2006
Program:
STTR
Phase:
Phase I
Contract:
W911NF-06-C-0129
Agency Tracking Number:
A064-008-0026
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
ACHRONIX SEMICONDUCTOR LLC
95 Brown Road, Ithaca, NY, 14850
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
150069503
Principal Investigator:
Clinton Kelly, IV
(607) 351-3668
clint@achronix.com
Business Contact:
John Holt
Chairman and Chief Executive Office
(607) 821-1751
john@achronix.com
Research Institution:
CORNELL UNIV.
Rajit Manohar
330 Rhodes Hall
Ithaca, NY, 14853
(607) 592-4539
Nonprofit college or university
Abstract
Large scale Wireless ad hoc networks are growing in use in both military and commercial environments. In the military environment, the Future Combat Systems (FCS) initiative will rely upon the Tactical Mobile Ad Hoc Communications Network (TMACN) for all communications between warfighters, manned and unmanned military equipment, and sensors. Simulation and performance estimation of the TMACN is of utmost importance to the design and eventual deployment of this mission-critical solution. The proposed innovation is a wireless MANET simulator consisting of a semiconductor-based highly-parallel multiprocessor asynchronous Network-on-a-Chip (NoC) and an associated software architecture to enable faster-than-realtime (FTR) simulation of ad hoc networks with many thousands of nodes. By leveraging an existing NoC prototype, built in 2005 by the PI and Cornell University in a 0.18ìm CMOS process, and the existing software environment, we will develop an architecture design for a scalable hardware architecture and an associated software environment to simulate large TMACNs. We will then perform a detailed scalability analysis and trade-off analysis to assist in the development of a software design and low cost highly parallel multiprocessor-based single-chip hardware platform for a 90nm prototype in Phase II that will support several hundred to several thousand node TMACNs.

* information listed above is at the time of submission.

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