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Superconducting Parametric Amplifier

Award Information
Agency: Department of Defense
Branch: Army
Contract: W911NF-14-P-0026
Agency Tracking Number: A14A-010-0108
Amount: $149,999.00
Phase: Phase I
Program: STTR
Solicitation Topic Code: A14A-T010
Solicitation Number: 2014.A
Timeline
Solicitation Year: 2014
Award Year: 2014
Award Start Date (Proposal Award Date): 2014-08-28
Award End Date (Contract End Date): 2015-02-26
Small Business Information
175 Clearbrook Road
Elmsford, NY -
United States
DUNS: 103734869
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Deepnarayan Gupta
 Executive Vice President
 (914) 592-1190
 gupta@hypres.com
Business Contact
 Philip Puma
Title: Contract Administrator
Phone: (914) 592-1190
Email: ppuma@hypres.com
Research Institution
 MIT Lincoln Laboratory
 Michael McElman
 
244 Wood Street Technology&Contracts Office
Lexington, MA 02420-9108
United States

 (781) 981-6048
 Federally funded R&D center (FFRDC)
Abstract

HYPRES, in collaboration with MIT Lincoln Laboratory and ISQC, proposes to transition superconducting parametric amplifier technology into a robust line of products. In Phase I, we will develop three varieties of superconducting low-noise amplifiers (LNAs) in compact cryogenic microwave packages. These are two types of standing wave devices, lumped-element Josephson parametric amplifier (LJPA) and Josephson parametric converter (JPC), and a traveling wave parametric amplifier (TWPA). To address the primary application of real-time measurements of quantum circuits, the LNAs will be experimentally evaluated, characterized and demonstrated by integrating with quantum bits for their readout. Our plan is to expand the single-channel amplifier product to accommodate the growing complexity of quantum computing and cryogenic detector systems in Phase II. Working towards this goal, we will experimentally perform direct digitization of the LNA output at 4K in Phase I itself with existing superconductor analog-to-digital converter (ADC) chips, and evaluate sensitivity and bandwidth trade-offs. This will be accomplished by leveraging the complete digital data acquisition and processing infrastructure from HYPRES"cryocooled digital-RF receiver product. These data will be used to design an optimized product, enabling simultaneous multiplexed readout of multiple weak analog signals originating at cryogenic temperatures.

* Information listed above is at the time of submission. *

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