Low Power, Radiation Hardened Embedded Memory Compiler

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA9453-10-M-0157
Agency Tracking Number: F093-084-1908
Amount: $99,968.00
Phase: Phase I
Program: SBIR
Awards Year: 2010
Solicitation Year: 2009
Solicitation Topic Code: AF093-084
Solicitation Number: 2009.3
Small Business Information
4775 Centennial Boulevard, Suite 130, Colorado Springs, CO, 80919
DUNS: 619085371
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 John Bailey
 Sr Design Engineer
 (505) 294-1962
Business Contact
 Karen Cura
Title: Chief Financial Officer
Phone: (719) 531-0805
Email: karen.vancura@micro-rdc.com
Research Institution
Micro-RDC will develop a low power, radiation hardened memory compiler suitable for use in current and future satellite missions. The memory compiler will generate embedded memory blocks hardened against Total Ionizing Dose effects, Single Event Upsets, Single Event Latch-up, and Single Event Transients. The memory compiler supports a variety of different attributes including word length, aspect ratio, and memory types for several foundry processes and feature sizes to meet various application and radiation requirements. The IBM 90nm 9SF and 9LP (Low Power) CMOS processes are supported to provide a MegaRAD level Radiation Hardened-By-Design solution in a standard commercial foundry. The memory compiler provides the flexibility to lower Total Ionizing Dose tolerance of the design to gain higher performance with smaller area penalties in these processes. These embedded SRAM blocks have been fabricated and verified to meet the radiation hardened levels of this solicitation. The IBM 45nm 12SOI process is also supported to provide an advanced deep sub-micron SOI commercial foundry solution. For a hardened by process solution the memory compiler supports the BAE Systems Radiation Hardened RH15 CMOS process. The Micro-RDC compiler will supply all of the Computer Aided Design (CAD) files required to integrate with standard ASIC design flows. BENEFIT: High performance ASICs are expected to provide most of the processing functions in advanced satellite systems. These devices require large amounts of on-chip memory to prevent memory bandwidth limitations from stalling the processors. In the commercial realm, memory compilers are used to quickly and automatically design embedded memory blocks with a variety of different attributes including word size, aspect ratio, memory type, access time, and power dissipation. ASICs for space applications are not supported by standard commercial memory compilers. This is due to the complications associated with developing compilers to incorporate the unique aspects of space electronics such as radiation hardness, low power, and reliability. The Low Power, Radiation Hardened Memory Compiler developed under this effort provides a cost effective means for system designers to develop Radiation Hardened ASICs for space systems. Micro-RDC will enhance and maintain the Radiation Hardened Embedded Memory Compiler as fabrication technologies advance funding these activities out of commercial sales. This will provide an up-to-date compiler independent of fabrication facility that keeps to date with cost-effective volume of scale manufacturing for Radiation Hardened Embedded Memory.

* Information listed above is at the time of submission. *

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