Deep Submicron Radiation Hardened Logic for Communications

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA9453-10-C-0041
Agency Tracking Number: F083-204-0965
Amount: $748,809.00
Phase: Phase II
Program: SBIR
Awards Year: 2010
Solicitation Year: 2008
Solicitation Topic Code: AF083-204
Solicitation Number: 2008.3
Small Business Information
Microelectronics Research Development Co
4775 Centennial Boulevard, Suite 130, Colorado Springs, CO, 80919
DUNS: 619085371
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Steve Philpy
 Director of Programs
 (719) 531-0805
Business Contact
 Karen Cura
Title: Chief Financial Officer
Phone: (719) 531-0805
Research Institution
The development of advanced microelectronics for satellite communications applications have become increasingly expensive. Smaller feature-sized microelectronics fabrication is now needed to provide ICs for complex radiation-hardened communications systems operating in space. Historically, radiation-hardened integrated circuit (IC) components have been fabricated at dedicated foundries using specialty, hardened, larger-feature size, expensive processes while commercial foundries focus on producing high-performance, non-radiation tolerant, ICs using smaller and smaller feature size processes. Micro-RDC, a leading developer of technology for IC device hardening by design, instead of by process, has developed a family of 90nm Design-Hardened Structured Application Specific Integrated Circuits (DH SASICs) that can be produced on a commercial IC fabrication line using a Single Reticle, Multi-Project-Wafer. This enables satellite systems designers to develop high-performance radiation-hardened ICs, at a very low cost. This technology has gained much popularity lately amongst space communications IC designers, but the need for even higher speed devices now exists. This Phase II effort proposes to design, fabricate and test a proof-of-concept test chip to verify some of the key elements of a next generation 45nm SOI DH SASIC. This verification should demonstrate sufficient reduced program risk to entice an outside investor/developer to fund a Phase III development program. BENEFIT: Space Communications program designers are developing high-performance systems to provide advanced processing from space-based platforms. These systems require advanced, high-speed, radiation-hardened integrated circuits for data processing. High-Speed integrated circuits for specific processing functions that are radiation-hardened for space, currently either do not exist or are manufactured at great expense. These devices also tend to be large and require much power for operation. Commercial ICs are not tolerant to radiation effects and were not designed to meet military specifications. Micro-RDC’s previous 90nm Bulk CMOS Design-Hardened Structured ASIC program enables designers to develop advanced radiation-hardened digital ICs at a fraction of the cost and with much lower power demands. With even faster and more dense satellite system requirements now being developed Micro-RDC’s Design-Hardened Structured ASIC program needs to migrate to the next generation 45nm feature-size technology to meet the needs of even faster computing, with the benefit of SOI substrates for enhanced hardness.

* information listed above is at the time of submission.

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