Massively Parallel Processing for Image Processing

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N/A
Agency Tracking Number: 32651
Amount: $69,991.00
Phase: Phase I
Program: SBIR
Awards Year: 1996
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
A & O, Inc.
1453 Beulah Road, Vienna, VA, 22182
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Terence W. Barrett
 (703) 759-4518
Business Contact
Phone: () -
Research Institution
N/A
Abstract
The project addresses the development of a 64K Massively Parallel P rocessor (MPP) accelerator board together with OS software for installation on a HP-748 workstation providing generation of real-time, high-fidelity, high pixel density and high refresh rate graphic images. The MPP board will be based on associative string processors (ASPs) in a modular massively parallel computer (MPC) architecture. The architecture enables both (a) associative processing, using associative elements to achieve arithmetic match operations, and (b) high-density merging and matching of processors is both a SIMD and MIMSIMD design, removes the three bottlenecks associated with (1) limitations in input/output bandwidth; (2) instruction calls, and (3) image processing. An MPC design has previously been completed for the HP-747 workstation and Phase I of the project will (a) adapt that design to the HP-748 workstation, and address (b) linking the MPC OS software to REsearch Systems Inc.'s (RSI's) IDL image handling software environment and (c) Naval simulation and training needs. ASP chip modules have been fabricated at a number of foundries and 4K and 16K processor boards for sensor processing applications are already completed. In Phase II the 64K processor board will be fabricated and tested on an HP-748 workstation running Naval training and simulation software in the IDL environment.

* information listed above is at the time of submission.

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