Massively Parallel Processing for Image Processing
Department of Defense
Agency Tracking Number:
Solicitation Topic Code:
Small Business Information
A & O, Inc.
1453 Beulah Road, Vienna, VA, 22182
Socially and Economically Disadvantaged:
Terence W. Barrett
AbstractThe project addresses the development of a 64K Massively Parallel P rocessor (MPP) accelerator board together with OS software for installation on a HP-748 workstation providing generation of real-time, high-fidelity, high pixel density and high refresh rate graphic images. The MPP board will be based on associative string processors (ASPs) in a modular massively parallel computer (MPC) architecture. The architecture enables both (a) associative processing, using associative elements to achieve arithmetic match operations, and (b) high-density merging and matching of processors is both a SIMD and MIMSIMD design, removes the three bottlenecks associated with (1) limitations in input/output bandwidth; (2) instruction calls, and (3) image processing. An MPC design has previously been completed for the HP-747 workstation and Phase I of the project will (a) adapt that design to the HP-748 workstation, and address (b) linking the MPC OS software to REsearch Systems Inc.'s (RSI's) IDL image handling software environment and (c) Naval simulation and training needs. ASP chip modules have been fabricated at a number of foundries and 4K and 16K processor boards for sensor processing applications are already completed. In Phase II the 64K processor board will be fabricated and tested on an HP-748 workstation running Naval training and simulation software in the IDL environment.
* information listed above is at the time of submission.