Ultrathin BESOI for Fully Depleted CMOS Applications
Department of Defense
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Small Business Information
425 Lakeside Drive, Sunnyvale, CA, 94086
Socially and Economically Disadvantaged:
Everett E. King
AbstractBESOI fabrication techniques will be evaluated to select an optimum approach for manufacturing ultrathin silicon films on 150- and 200-mm diameter wafers. A supplier of such BESOI material will be identified. The baseline will be the SiGe etch stop and strain-sensitive etch method which ARACOR has already demonstrated to be capable of producing defect-free, undoped films that are as thin as 1000 angstrom on 100-mm wafers. ARACOR will demonstrate this BESOI process on 150-mm wafers in Phase I. In addition, a fully-depleted CMOS process flow for ultrathin SOI material, a suitable circuit to demonstrate this process, and a test matrix to validate the process and circuit will also be defined for subsequent use in the Phase II program. An option for Phase I will be to fabricate the 150-mm BESOI substrates needed to begin circuit processing in Phase II.
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