Ultra High Speed Analog to Digital Converter

Award Information
Agency:
Department of Energy
Branch
n/a
Amount:
$750,000.00
Award Year:
2004
Program:
SBIR
Phase:
Phase II
Contract:
DE-FG02-03ER83597
Award Id:
61847
Agency Tracking Number:
72181S03-I
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
28119 Ridgefern Court, Rancho Palos Verdes, CA, 90275
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Vladimir Katzman
Dr.
(310) 377-6029
traffic405@cox.net
Business Contact:
Vladimir Katzman
Dr.
(310) 377-6029
traffic405@cox.net
Research Institution:
n/a
Abstract
72181-Current and proposed Nuclear Physics (NP) experiments require very accurate measurement of very short-lived phenomena at a very large number of very close measurement locations. Available data acquisition systems use currently available analog-to-digital converter (ADC) technologies, which cannot be packed densely enough to extract all of the available information from these experiments. Current ADC data transfer speeds, power consumption, pin count, and mutual electromagnetic interference levels have compromised the ability to measure and understand many small-scale phenomena. This project will develop a new architecture that combines a proprietary high-speed (500 Ms/s), high-resolution, flash/folding ADC core with a proprietary high speed (up to 30 GB/s), multi-level (ternary) serializer/deserializer (SERDES) interface. Phase I developed the ADC architecture, performed computer simulations of the basic ADC blocks, and proved the feasibility of the proposed concept. The computer simulation indicated a maximum data rate of 30 Gb/s at the high-speed digital ADC output. A bench prototype of the ternary interconnect, based on off-the-shelf components and operating at 12 Gb/s, was demonstrated. In Phase II, the ADC and SERDES will be integrated into a set of mixed-signal ICs, which will be manufactured using an advanced commercial high density SiGe fabrication process. Phase II, will design and fabricate ADC and SERDES Application Specific Integrated Circuits (ASICs) and integrate the developed product into a functional data acquisition system. Commercial Applications and Other Benefits as described by awardee: The technology should reduce complexity and improve the performance of next generation data acquisition systems used in a variety of experiments at multiple DOE research facilities. Other applications include homeland security, wireless ground station, medical image processing, telecommunications, and process control.

* information listed above is at the time of submission.

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