Bit Transparent Ternary SERDES for Intra-System Data Transfer

Award Information
Agency:
National Aeronautics and Space Administration
Branch:
N/A
Amount:
$69,909.00
Award Year:
2003
Program:
SBIR
Phase:
Phase I
Contract:
NAS5-03029
Agency Tracking Number:
022293
Solicitation Year:
N/A
Solicitation Topic Code:
N/A
Solicitation Number:
N/A
Small Business Information
Advanced Science and Novel Technology
28119 Ridgefern Court, Rancho Palos Verdes, CA, 90275
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
N/A
Principal Investigator
 Vladimir Katzman
 Principal Investigator
 (310) 377-6029
 traffic405@cox.net
Business Contact
 Vladimir Katzman
Title: President
Phone: (310) 377-6029
Email: traffic405@cox.net
Research Institution
N/A
Abstract
Serializer/Deserializer (SERDES) components are the key components for high speed serial data transfer. Low latency, high bandwidth communications between processor nodes with upgrade ability within a box is of utmost importance in advanced NASA communication systems. Parallel architectures represent a bottleneck in terms of bandwidth and pin count. Several new standards such as Infiniband, Hypertransport, 3GIO, and RapidIO are evolving with a common direction towards serial system interconnect for next generation back-plane developments. Commercially available SERDES to support new standards have well known bit ambiguity at the deserializer output thereby requiring additional circuitry as well as software to solve this problem.In order to overcome the bit ambiguity problem, Advanced Science and Novel Technology (ADSANTEC) proposes a novel ternary SERDES technique. The technique uses a ternary signal at the Serializer (SER) output to mark a reference bit position. The marked bit positions are used to recover a low-speed clock signal for receiver word alignment using a clock multiplier technique. The proposed concept will lead to the development of a new generation of serial data interconnect. ADSANTEC?s innovative solution will offer high throughput (up to 50Gb/s) and eliminate latency introduced by the switching fabric of existing digital interconnect approaches.

* information listed above is at the time of submission.

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