Switching Fabric Based on Multi-Level LVDS Compatible Interconnect

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNG05CA10C
Agency Tracking Number: 033192
Amount: $599,987.00
Phase: Phase II
Program: SBIR
Awards Year: 2005
Solicitation Year: 2003
Solicitation Topic Code: E2.03
Solicitation Number: N/A
Small Business Information
Advanced Science and Novel Technology
28119 Ridgefern Court, Rancho Palos Verdes, CA, 90275-2049
DUNS: 114422095
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Vladimir Katzman
 Principal Investigator
 (310) 377-6029
Business Contact
 Vladimir Katzman
Title: President
Phone: (310) 528-2532
Email: traffic405@cox.net
Research Institution
Switching fabric (SF) is the key component of the next generation of back plane interconnects. Low power, TID and SEU resistant and high bandwidth upgradeable communication between computer nodes are of utmost importance for future NASA missions. The current state off-the-art binary SF interconnect architectures have high power consumption and latency due to the necessity to perform internal data conversion and synchronization in order to recognize redundant bits and extract useful information from the data stream. The high power consumption of the SFs limit their application in the next generation of nano-satellites. In order to minimize latency and reduce power consumption, we propose a novel, robust, radiation tolerant and easy-to-align SF based on a multi-level power efficient Low Voltage Differential Signal interface. Our approach uses differential multilevel signals to mark a reference high-level bit position in one of the differential channels. Because the marked pilots will follow the high logic level in one of the differential outputs, they will regularly occur at the same bit position and ensure stable and easy recovery of the low-speed clock signal, which will be used as a reference for multi-channel data alignment and will synchronize high speed clocking circuitry using a standard clock multiplier technique.

* information listed above is at the time of submission.

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