Low Power Ultra-Fast Analog-to-Digital Converter with Integrated DSP

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA9453-05-M-0092
Agency Tracking Number: F051-019-2288
Amount: $100,000.00
Phase: Phase I
Program: SBIR
Awards Year: 2005
Solicitation Year: 2005
Solicitation Topic Code: AF05-019
Solicitation Number: 2005.1
Small Business Information
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275
DUNS: 114422095
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Vladimir Katzman
 (310) 377-6029
Business Contact
 Vladimir Katzman
Title: President
Phone: (310) 377-6029
Email: traffic405@cox.net
Research Institution
The front end digital processing of a communications satellite/warfighter typically consists of an analog-to-digital converter (ADC) followed by a demodulator and Digital Signal Processor (DSP). The integration of both functions in an ADC/DSP monolithic Integrated Circuit (ADIC) is an effective way to overcome the difficulties associated with propagation delays and transmission line effects in the required high-speed parallel interconnects between the ADC and the DSP application specific integrated circuits. In order to satisfy the described need, our company in cooperation with the Georgia Tech University team under management of Byers Professor John Cressler proposes to develop a novel ADIC architecture based on a proprietary, extremely low power, 2.5 Gs/s ADC block, which will be implemented in one of the most advanced modern SiGe technologies. ADIC architectures with either an analog demultiplexing scheme based on a proprietary dual-bridge sample-and-hold amplifier (SHA), or a high-speed SHA and a signal splitter will be evaluated in order to select the best design approach.. The required reduction of supply voltage and power consumption will be achieved at the basic cell hierarchical level through application of the fully differential bipolar-based current-mode logic or MOS-based source-coupled logic with ADSANTEC's proprietary voltage referencing scheme.

* information listed above is at the time of submission.

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