High Performance Rad Hard Analog to Digital Converter Architectures

Award Information
Agency: Department of Defense
Branch: Missile Defense Agency
Contract: HQ0006-08-C-7804
Agency Tracking Number: B073-003-0208
Amount: $99,999.00
Phase: Phase I
Program: SBIR
Awards Year: 2008
Solicitation Year: 2007
Solicitation Topic Code: MDA07-003
Solicitation Number: 2007.3
Small Business Information
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275
DUNS: 114422095
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Sean Woyciehowsky
 Director ASIC Design
 (408) 564-9236
Business Contact
 Vladimir Katzman
Title: President
Phone: (310) 377-6029
Email: vkatzman@adsantec.net
Research Institution
Electronic components for future space based radar systems on chip (SOC) must function correctly in natural and radiation filled environments while providing state-of-the-art performance. The corresponding SOC must employ advanced, extra low-power, radiation-hardened (RH), analog-to-digital converters (ADCs) capable of operating at multi-giga sampling speeds. To satisfy the described needs, we propose to develop an ADC block with 9 bits of resolution and up to 10Gs/s of sampling speed. The 9 bit wide data will be demultiplexed by a factor of eight to a rate of 1.25Gb/s for direct loading into a following FPGA where signal processing will be performed. Our patent-pending radiation-hardening techniques incorporate a methodology based on protection and redundancy, which provides both total ionization dose (TID) and single-event upset (SEU) tolerance within the IC. The proposed high performance characteristics of the ADC will be achieved by utilizing an advanced SiGe IC fabrication technology.

* Information listed above is at the time of submission. *

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