Extremelly High Bandwidth Rad Hard Data Acquisition System

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNC07QA67P
Agency Tracking Number: 066680
Amount: $69,990.00
Phase: Phase I
Program: SBIR
Awards Year: 2007
Solicitation Year: 2006
Solicitation Topic Code: S4.01
Solicitation Number: N/A
Small Business Information
ADVANCED SCIENCE AND NOVEL TECHNOLOGY
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275-2049
DUNS: 114422095
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Sean Woyciehowsky
 Principal Investigator
 (310) 377-6029
 woycieho@sbcglobal.net
Business Contact
 Vladimir Katzman
Title: Business Official
Phone: (310) 377-6029
Email: traffic405@cox.net
Research Institution
N/A
Abstract
Advancements in sensors/detectors are needed to support future NASA mission concepts including polarimetry, large format imaging arrays, and high-sensitivity spectroscopy. The corresponding data acquisition systems must employ high-speed, extra low power, linear analog-to-digital converters (ADCs) featuring a wide input bandwidth and reasonable effective number of bits, followed by a digital signal processor usually implemented inside a field-programmable gate array with a relatively low-speed data interface. In addition, radiation tolerance represents one of the main requirements for the space-oriented electronics. Commercially available ADCs feature high power consumption, high latency, poor linearity, and low radiation tolerance at high input bandwidths above 1GHz. To address the described needs, we propose a novel, low-power, high input bandwidth, radiation-tolerant, under sampling ADC with an output digital demultiplexer that enables direct data loading into a standard FPGA. Wide input bandwidth, low input return loss, 6-bit accuracy, low distortion and power consumption will be achieved through utilization of a proprietary adaptive matching filter and dual-output sample-and-hold amplifier followed by two reduced-rate ADCs. The digitized signals are delivered to the proprietary low-power LVDS output buffers after rate adjustment and realignment to the selected clock signal. Advanced technology featuring heterojunction bipolar transistors will provide the required radiation tolerance.

* information listed above is at the time of submission.

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