Fast Low Power ADC with Integrated Digital Data Processor

Award Information
Agency:
National Aeronautics and Space Administration
Branch
n/a
Amount:
$69,999.00
Award Year:
2007
Program:
SBIR
Phase:
Phase I
Contract:
NNX07CA69P
Agency Tracking Number:
065570
Solicitation Year:
2006
Solicitation Topic Code:
S6.04
Solicitation Number:
n/a
Small Business Information
ADVANCED SCIENCE AND NOVEL TECHNOLOGY
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275-2049
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
114422095
Principal Investigator:
Vladimir Bratov
Principal Investigator
(310) 528-9118
bratov@comcast.net
Business Contact:
Vladimir Katzman
Business Official
(310) 377-6029
traffic405@cox.net
Research Institution:
n/a
Abstract
Innovative data measurement/acquisition systems are needed to support future Earth System Science measurements of the Earth's atmosphere and surface. An adequate system must employ a high-speed, extra low power, linear, analog-to-digital converter (ADC) with high input bandwidth and accuracy, followed by a digital signal processor that is usually implemented inside a field-programmable gate array (FPGA). Commercially available ADCs with input bandwidths larger than 1GHz feature high power consumption and latency, and poor linearity. With increasing ADC sampling rates, timing difficulties within the parallel interconnects between the ADC and the following FPGA become increasingly prominent. Therefore, a monolithic ADC incorporating a data converter that performs digital data demultiplexation and retiming is desired. To address these needs, the Advanced Science and Novel Technology Company proposes to develop a novel, extra low-power, extremely linear, under-sampling ADC featuring a high analog input bandwidth (>5GHz) that can easily interface to a following FPGA through a low-speed (<750Mb/s) parallel interface. To achieve this functionality, the proposed system-on-chip will utilize a proprietary sub-Nyquist front-end analog demultiplexer, a combinational ADC structure with proprietary gain-stabilization circuitry, and a digital signal processor implementing digital data demultiplexation and the company's proprietary data alignment scheme.

* information listed above is at the time of submission.

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