A VLSI NEUROCOMPILER FOR MASSIVELY INTERCONNECTED MODELS

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N/A
Agency Tracking Number: 12172
Amount: $59,034.00
Phase: Phase I
Program: SBIR
Awards Year: 1990
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
5113 Leesburg Pike - Ste 514, Falls Church, VA, 22015
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Duane R Ball
 (703) 845-0041
Business Contact
Phone: () -
Research Institution
N/A
Abstract
MASSIVELY INTERCONNECTED COMPUTERS, COMMONLY CALLED NEUROCOMPUTERS, ARE AT THE HEART OF SIXTH-GENERATION COMPUTING. TO DATE, HOWEVER, ONLY NEUROCOMPUTER SIMULATORS AND EMULATORS ARE AVAILABLE. THIS RESEARCH PROJECT WILL DEVELOP TOOLS AND TECHNIQUES TO TRANSLATE NEUROCOMPUTERS INTO COMPUTATIONALLY EQUIVALENT DIGITAL VLSI CIRCUITS. CONCEPTS FROM SWITCHING CIRCUIT THEORY WILL BE USED TO TRANSLATE INDIVIDUAL NODES OR GROUPS OF NEUROCOMPUTER NODES INTO AN EQUIVALENT DIGITAL CIRCUIT. A STOCHASTIC OPTIMIZATION TECHNIQUE, BASED ON THE GENETIC ALGORITHM, WILL BE DEVELOPED TO TRANSFORM THE DIGITAL LOGIC CIRCUIT SO THAT IT MEETS ANALYST SPECIFIED AREA AND RESPONSE-TIME REQUIREMENTS. THE DEGREE OF FAULT-TOLERANCE REQUIRED BY THE ANALYST WILL BE ADDED INTO THE DESIGN USING TECHNIQUES FROM CODING THEORY. THE TOOL DEVELOPED DURING THIS RESEARCH, CALLED A NEUROCOMPILER, WILL GENERATE VHDL DESCRIPTIONS OF THE RESULTING DESIGNS SO THAT SILICON COMPILERS CAN COMPLETE THE TECHNOLOGY DEPENDENT (E.G., CMOS) ELEMENTS OF THE DESIGN. THE NEUROCOMPILER WILL ALSO INTERFACE WITH CHIP PROGRAMMERS AND PRINTED CIRCUIT BOARD DESIGNERS FOR SMALLER SCALE CHIP PRODUCTION.

* Information listed above is at the time of submission. *

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