Modular, Fault-Tolerant Electronics Supporting Space Exploration

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNJ07JA09C
Agency Tracking Number: 053820
Amount: $599,925.00
Phase: Phase II
Program: SBIR
Awards Year: 2007
Solicitation Year: 2005
Solicitation Topic Code: X1.01
Solicitation Number: N/A
Small Business Information
20145 Ashbrook Place, Ashburn, VA, 20147-3373
DUNS: 605603984
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Frank LaRosa
 Principal Investigator
 (727) 581-3773
Business Contact
 Kim Irving
Title: Business Official
Phone: (703) 554-6335
Research Institution
Modern electronic systems tolerate only as many point failures as there are redundant system copies, using mere macro-scale redundancy. Fault Tolerant Electronics Supporting Space Exploration (FTESSE) creates an electronic design paradigm using reprogrammable FPGAs to create swappable Circuit Object Blocks (COBs) – analogous to software objects – for the first time enabling redundancy on a micro-scale. The result is an increased tolerance of point failures by several orders of magnitude over traditional approaches. In the FTESSE approach, FPGAs are partitioned into COBs (groups of gates), each performing a specific function. Bad areas can be mapped like the bad sector data on a disk drive, enabling COBs to be placed in areas of working gates to recover system performance. Hardware tested during Phase I verified point failures could be introduced into an example circuit and corrected. As in the Phase I model, circuits to be monitored reside on a Slave FPGA, and a Master FPGA monitors outputs of all COBs, sensing faults and mapping non-working gates on the Slave FPGA. The Master is a rad-hard, triple mode redundancy (TMR) FPGA, but the Slaves need not be, opening the doors to higher performance applications while maintaining high levels of fault tolerance.

* Information listed above is at the time of submission. *

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