A Multi-Level Secure High-Speed Shared Memory Interconnect

Award Information
Agency:
Department of Defense
Branch
Navy
Amount:
$79,858.00
Award Year:
2004
Program:
SBIR
Phase:
Phase I
Contract:
N68936-05-C-0010
Agency Tracking Number:
N043-243-0962
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
AERONIX, INC.
1775 W. Hibiscus Blvd., Suite 200, Melbourne, FL, 32901
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
151118650
Principal Investigator:
Geoff Miller
Systems Engineer
(321) 984-1671
gmiller@aeronix.com
Business Contact:
Ron Capasso
Vice President
(321) 984-1671
rcapasso@aeronix.com
Research Institution:
n/a
Abstract
The military and intelligence communities seek computing systems that can safely share information with different degrees of confidentiality. Systems achieving that goal are said to operate in multi-level mode, which indicates that the system contains information at several different levels of confidentiality but cannot share information with unauthorized users. Communities requiring multi-level systems also demand a high level of confidence that they operate correctly, since leaked intelligence data could potentially destroy the effectiveness of extremely expensive intelligence gathering systems. A system or device achieves the objective of being "multilevel secure" if it can handle information at a variety of sensitivity levels without disclosing information to an unauthorized person. Implementations of fabric based solutions include processing elements that also contain direct memory access (DMA) nodes. These are programmable, such that data movements between processing elements of data residing within memory systems local to each processing are handled by the nodes and switched fabric crossbars. Aeronix is proposing to develop a high assurance, Multi-level secure, high speed, shared memory interconnect system capable of accreditation by NSA and/or other agencies. The main component of the system is a modified interconnect system architecture such as Rapid -IO, modifications will address multi-level security, use of shared-memory, and high assurance.

* information listed above is at the time of submission.

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