Secure Trusted Computing System-on-Chip
Department of Defense
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AbstractMany currently fielded DoD electronic systems contain sensitive and sometimes classified software applications. These sophisticated systems incorporate embedded COTS processing devices which make them susceptible to reverse engineering using commercial off the shelf tools including emulators and debuggers. To address this problem, various anti-tamper techniques have been employed. Traditionally, these have been either at the device level or at the card/box boundary level. Each of these approaches has its benefits and drawbacks. Chip level coatings can be costly to apply, due to the special procedures and process steps outside of the normal semi-conductor fabrication flow. They also tend to have higher yield losses caused by the protective technology itself. These coatings are limited to protecting the sensitive information contained within a single device (or within a protected cavity such as a multi chip module). On the other hand, card and box level tamper mechanisms protect the information flow within a larger area of interest. Their limitation is that if an adversary is able to circumvent the tamper mechanism, all internal information is then available. The specific problem addressed by this SBIR is the protection of sensitive or classified information flowing between devices within a card and or a collection of circuit cards (e.g. box, sub-system, system). A family of system on a chip (SOC) components will be developed to support this paradigm. These devices will incorporate many of the Crypto Modernization tenets identified and developed by the NSA. The devices will be fabricated using the DoD/NSA sponsored trusted foundry facilities. They will be referred to throughout this proposal as the Trusted System on a Chip (TSOC).
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