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Low-Latency Embedded Vision Processor (LLEVS)

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA8650-15-M-6657
Agency Tracking Number: F15A-T13-0209
Amount: $149,999.00
Phase: Phase I
Program: STTR
Solicitation Topic Code: AF15-AT13
Solicitation Number: 2015.1
Timeline
Solicitation Year: 2015
Award Year: 2015
Award Start Date (Proposal Award Date): 2015-08-03
Award End Date (Contract End Date): 2016-04-29
Small Business Information
535 W. Research Center Blvd., Fayetteville, AR, 72701
DUNS: 968358452
HUBZone Owned: Y
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Parviz Palangpour
 Chief Technology Officer
 (479) 571-2592
 parviz@nanowattdesign.com
Business Contact
 Mark Kidd
Phone: (479) 571-2592
Email: mark.kidd@nanowattdesign.com
Research Institution
 University of North Texas
 Joe Evans
 Hurley Administration Building
1501 W. Chestnut St.
Denton, TX, 76203-5017
 (940) 565-4596
 Domestic nonprofit research organization
Abstract
ABSTRACT: The goal of head-worn display systems is to increase situation awareness and reduce operator workload. The urgent need is for higher image resolution and lower system latency, while meeting constraints on head-borne weight and power. Current processor solutions cannot meet increased requirements. The challenge is that power consumption is proportional to the amount of data being handled, which increases along with higher resolution and faster frame rates. This Small Business Technology Transfer Phase I project is to develop detailed plans for a low-latency embedded processor having fundamentally reduced energy per operation, enabling implementation of the image processing algorithms required for a digital helmet-mounted display for dismounted soldiers. Two plans for designing a vision-processor helmet system in Phase II and fabricating the processor in Phase III will be developed during the Phase I project. A low-risk plan will be based on using existing, proven solutions to meet emerging requirements, while a high-risk plan will be based on applying solutions that are available today, but requires further proof for the embedded vision processor application. With both plans, power, latency, weight, and size of the processors and peripheral devices will be estimated. Risks and benefits associated with each approach will be clearly identified.; BENEFIT: Due to rapid improvements in camera technology, vision systems are now included in many defense applications, including those carried by the Soldier as well as fixed-position, unattended systems placed at key observation points. Development of a small, low power, image processor capable of faster processing of large video formats with sub-frame latency will be a critical enabler for many applications, including for example, unmanned air and ground vehicles, digital night vision, gun sights, wearable displays, and helmet mounted displays . The broad target market is embedded computation, with significant power savings gained by off-loading tasks from a general purpose processor to a dedicated multi-core image processor. The recent trend is to add embedded image processing to mobile systems, which dramatically increases required computation and leads to dramatic growth in power consumption. Commercial demand for a low-power, embedded image processor include a wide variety of end applications such as tablet, laptop, desktop and datacenter computers, mobile phones, video game consoles, high-speed communication devices, and graphics displays

* Information listed above is at the time of submission. *

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