Functional Dataflow Programming Toolchain for Portable Parallel Code

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: D15PC00140
Agency Tracking Number: D151-004-0093
Amount: $149,496.96
Phase: Phase I
Program: SBIR
Solicitation Topic Code: SB151-004
Solicitation Number: 2015.1
Timeline
Solicitation Year: 2015
Award Year: 2015
Award Start Date (Proposal Award Date): 2015-06-01
Award End Date (Contract End Date): 2016-05-31
Small Business Information
51 East Main Street, Newark, DE, 19711
DUNS: 071744143
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Paul Fox
 Senior Engineer
 (302) 456-9003
 fox@emphotonics.com
Business Contact
 Eric Kelmelis
Title: Dr.
Phone: (302) 456-9003
Email: kelmelis@emphotonics.com
Research Institution
N/A
Abstract
A new class of high-performance, low-SWaP computational devices is emerging based on increasingly diverse architectures. This diversity is improving performance, but comes at the cost of increased programming complexity. Each architecture requires variances in programming environment and model, typically distinguished by the type of parallelism supported by the hardware, limiting software portability. Portable parallelism can be realized with a toolchain utilizing a whole-program dataflow graph, containing all essential dependency information to ensure program correctness while providing maximum flexibility in scheduling operations. While it is infeasible to perform the analysis necessary for this approach in imperative languages like C, C++, and Java, pure functional languages like Scheme and Haskell contain explicit dependency information within the code. Therefore, we will develop a toolchain based on the Haskell language and compiler, using a dataflow graph as an intermediate representation of the program, and produce optimized code for different hardware platforms. This will permit software written in a simple declarative (functional) programming style to be automatically compiled and optimized for diverse architectures, including GPUs and FPGAs. The immediate application areas targeted by our toolchain will be real-time image processing and scientific computing with the potential to expand in the future.

* Information listed above is at the time of submission. *

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