Quantum Cryptography Single Photon Detector Chip

Award Information
Agency: Department of Defense
Branch: Defense Microelectronics Activity
Contract: HQ0727-15-P-1502
Agency Tracking Number: 15-5A6
Amount: $149,956.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: DMEA142-001
Solicitation Number: 2014.2
Timeline
Solicitation Year: 2014
Award Year: 2015
Award Start Date (Proposal Award Date): 2015-05-21
Award End Date (Contract End Date): 2015-12-15
Small Business Information
1900 S. Harbor City Blvd., Suite 236, Melbourne, FL, 32901
DUNS: 878400068
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Dr. Glenn Hess
 Chief Technical Officer
 (321) 727-0328
 ghess@aet-usa.com
Business Contact
 Mr. Thomas Sanders, Jr.
Title: Electronics Engineer
Phone: (321) 727-0328
Email: tjs@aet-usa.com
Research Institution
N/A
Abstract
AET will perform R&D to develop a quantum cryptographic single photon counting system (or detector) consisting of a high performance integrated circuit chip and detector (such as an avalanche photodiode) for use in a secure fiber optic communications link. Quantum cryptography applies an encryption scheme that uses a series of single, polarized photons that act as the key between the sender and receiver. If an eavesdropper or would-be hacker tries to intercept this key, these photons will immediately become corrupted, render the message unintelligible, and alert the sender and intended recipient to the spying attempt. Both users will postpone sending any valuable data until the optical link is secured. In Phase I, AET will identify the requirements for the Quantum Cryptography Single Photon Detector (QCSPD) System chip and perform a trade-off study of the various technologies considered. AET will initially identify the overall system requirements for the QCSPD and identify acceptable requirements for the optical fiber and detector. From here, AET will derive requirements for the silicon integrated circuit chip, which probably will use CMOS technology. Then a technology trade-off study will define the optimum technologies to employ and finally a chip architecture will be developed for the integrated circuit.

* Information listed above is at the time of submission. *

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