SBIR Phase II: High-Speed, Low-Cost Maskless Lithography

Award Information
Agency: National Science Foundation
Branch: N/A
Contract: 0620566
Agency Tracking Number: 0512972
Amount: $429,287.00
Phase: Phase II
Program: SBIR
Awards Year: 2006
Solicitation Year: 2004
Solicitation Topic Code: MI
Solicitation Number: NSF 04-604
Small Business Information
PO Box 11180, Jackson, WY, 83002
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Richard Yeh
 (307) 732-1994
Business Contact
 Mark Peterman
Title: Mr
Phone: (307) 732-1994
Research Institution
This Small Business Innovation Research (SBIR) Phase II project will research and develop a maskless lithography tool based on the results of the feasibility study. The company has a unique and proprietary approach to achieve higher throughput and lower cost than currently available maskless lithography tools. The approach will employ Line Light Modulator (LLM) to pattern wafers with a linear array of 2048 beams. The patent-pending LLM is a novel and efficient light engine that converts a single light source into a large linear array of beamlets. Using a large array of beamlets increases the power handling capability of the system which increases the exposure throughput. The result is a one to two order of magnitude improvement in throughput compared to existing maskless lithography tools. Our tool also takes advantage of the new 405nm diode laser. The 405nm diode laser offers a combination of power, cost, and speed not available in other UV laser sources. In the feasibility study, we have demonstrated the ability to pattern photoresist with <1um resolution using the LLM. In Phase II, we will develop and fully characterize a prototype tool that will achieve a 1um resolution, 50nm position accuracy, and a throughput of 65mm2/sec (two minutes per 4" wafer). As high volume semiconductor production has mostly moved overseas, the US semiconductor industry relies more on prototyping and initial manufacturing of innovative, cutting-edge technology. Lowering the cost to pattern wafers at these volumes helps keep US companies competitive by enabling rapid and cost-effective innovations. Cost is especially important for the small- to medium-sized companies that neither have the capital for high cost mask sets, nor require the most advanced resolutions of modern conventional lithography tools. The proposed tool addresses this need for fast and cost-effective semiconductor lithography with good throughput, resolution, and seamless integration with current lithography processes. The proposed project will provide researchers with an affordable tool to quickly fabricate new and existing designs. These low cost lithography tools will also be useful in fabrication and MEMS laboratory courses. A maskless lithography tool will make it practical for students to design and fabricate devices instead of simply using masks made for the course.

* information listed above is at the time of submission.

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