High Sensitivity Analog to Digital Converter for Wideband RF Signal

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N00014-08-M-0299
Agency Tracking Number: N08A-027-0368
Amount: $70,000.00
Phase: Phase I
Program: STTR
Awards Year: 2008
Solicitation Year: 2008
Solicitation Topic Code: N08-T027
Solicitation Number: 2008.A
Small Business Information
298 Janine Way, Bridgewater, NJ, 08807
DUNS: 824637685
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Jungsang Kim
 Nortel Networks Assistant Professor
 (919) 660-5258
Business Contact
 Wonsuck Lee
Title: Member
Phone: (908) 229-5966
Email: wlee@aletav.com
Research Institution
 Jungsang Kim
 ECE Department
Box 90291
Durham, NC, 27708
 (919) 660-5258
 Nonprofit college or university
With the advances in solid-state electronics and optoelectronics, ultra wideband radio frequency receiver designs are now practical. One of the consequences of these large bandwidth waveforms is the very high range resolution that results. Various architectures of receivers have been proposed for the ultra wideband applications, but most popular architectures among them are heterodyne, homodyne, low-IF and zero-IF. The receiver designs require large bandwidths to preserve signal waveforms and high-speed circuits for signal detection. Normally, the wideband signal components at the low and the high bounds are processed with different fidelity due to the difference in dispersion and loss. Additionally, the frequency-dependent wideband signal loss must be also addressed in the receiver design. The ultra wideband receiver must be equipped with high-performance analog-to-digital converters (ADCs). In receiver, extremely high sampling rate is required in order to preserve and repeat the wideband signal for digitizing. In light of this, we propose an ADC architecture which includes a novel analog signal pre-processing stage. Through the pre-processing stage, incoming signals are filtered and transformed at real time within analog RF domain. The proposed architecture enhances the robustness against noise and jitter, ultimately SNR and SFDR, for the high fidelity signal-to-information conversion.

* information listed above is at the time of submission.

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