AN 8-BIT GHZ DIGITIZER IS PROPOSED WITH A FRONT-END ANALOG DEMULTIPLEXTER USING GAAS SAMPLE-AND-HOLD CIRCUITS FOR CONVERTING THE INPUT SIGNAL DOWN TO 125 MHZ.

Award Information
Agency:
Department of Defense
Branch
Navy
Amount:
$49,964.00
Award Year:
1986
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Award Id:
3636
Agency Tracking Number:
3636
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
2239 Townsgate Rd - Ste 208, Westlake Village, CA, 91361
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
DR TEONG C LIM
(805) 495-9388
Business Contact:
() -
Research Institute:
n/a
Abstract
AN 8-BIT GHZ DIGITIZER IS PROPOSED WITH A FRONT-END ANALOG DEMULTIPLEXTER USING GAAS SAMPLE-AND-HOLD CIRCUITS FOR CONVERTING THE INPUT SIGNAL DOWN TO 125 MHZ. A BANK OF SILICON 80BIT 125-MHZ A/D CONVERTERS ARE THEN USED FOR SIGNAL DIGITIZATION. DIGITIZED DATA ARE FURTHER DEMULTIPLEXTED BEFORE STORING INTO ECL MEMORY. THE ADVANTAGES OF THE PROPOSED APPROACH ARE THAT: (1) THE REQUIRED GAAS CIRCUITS ARE MINIMAL AND THE PERFORMANCE OF THESE CIRCUITS HAVE BEEN DEMONSTRATED AND THE REST OF THE COMPONENTS FOR THE PROPOSED SYSTEM ARE ALL SILICON ICS WHICH ARE COMMERCIALLY AVAILABLE THUS RESULTING IN AN OVERALL LOW-RISK APPROACH, AND (2) THE PROPOSED ARCHITECTURE ALLOWS FUTURE EXTENSION TO A LONGER SAMPLE WINDOW, HIGHER BIT ACCURACY, AND HIGHER SAMPLING FREQUENCIES. PHASE I PROGRAM WILL PROVIDE A DETAILED ANALYSIS OF SYSTEM DESIGN AND COMPUTER SIMULATED CIRCUIT DESIGN WHICH WILL BE USED FOR IC FABRICATION AND BREADBOARDING IN PHASE II.

* information listed above is at the time of submission.

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