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Open|SpeedShop Ease of Use Performance Analysis for Heterogenious Processor Systems

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX15CA14C
Agency Tracking Number: 144669
Amount: $745,213.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: S5.01
Solicitation Number: N/A
Timeline
Solicitation Year: 2014
Award Year: 2015
Award Start Date (Proposal Award Date): 2015-05-29
Award End Date (Contract End Date): 2017-05-28
Small Business Information
999 Windcroft Plaza
Annapolis, MD 21401-6578
United States
DUNS: 964379965
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 James Galarowicz
 Computer Scientist
 (612) 644-3303
 JEGKAS@gmail.com
Business Contact
 Tom Brennan
Title: Business Official
Phone: (515) 598-2722
Email: tjmbrennan@gmail.com
Research Institution
N/A
Abstract

We propose building upon the modular extensible architecture and existing capabilities of Open|SpeedShop to provide seamless, integrated, heterogeneous processor performance analysis. The NVIDIA GPU and Intel Many Integrated Core (MIC) processors are increasingly important at high performance computing (HPC) laboratories within NASA for use on NASA's high-end computing (HEC) projects because of their ability to accelerate scientific application performance. In order to understand what impact these accelerators are having on performance, tools must succinctly present heterogeneous processor performance information.

One of the key goals of this work is to develop and implement innovative methods for presenting the performance information extracted from applications running on both traditional CPU and GPU/MIC processors.

Phase II research builds on the progress made in phase I and will include more robust and complete gathering performance information for Intel's MIC architecture. In phase I we built the infrastructure and successfully prototyped a version of Open|SpeedShop that gathered and displayed performance information for applications that ran in the non-offload Intel MIC programming model. For phase II, our research would focus on how to monitor the performance of applications that use Intel's offload programming model. We would also focus research into performance analysis for applications using OpenACC.

* Information listed above is at the time of submission. *

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