American Semiconductor, Inc.

Basic Information

3100 S. Vista Ave., Suite 230
Boise, ID, 83705-

Point of Contact Information

Field Value
Business Official:
Firm CFO (or equivalent):
POC Contracting Officer (or equivalent)

Additional Details

Field Value
SBC Control ID: SBC_000000382
DUNS: 76338677
SIC Codes: n/a
NAICS Codes: n/a

Company Profile


  1. Enabling Flexible Materials, Devices and Processes for Defense

    Amount: $749,995.00

    ABSTRACT: Emergence and feasibility for flexible body-worn electronics and particularly medical patches requires high performance electronics capability. The problem is that these new technologies m ...

    SBIR Phase II 2014 Air ForceDepartment of Defense
  2. FleX-3D Wafer Processing for Chip Stacking and Interconnect

    Amount: $149,977.00

    Reliable, readily-manufacturable technologies are needed to create the next generation of high-density, high-functionality 3D integrated circuits (ICs) for integrating silicon pixel detectors with CMO ...

    SBIR Phase I 2013 Department of Energy
  3. A 45 nm Low Cost, Radiation Hardened, Platform Based Structured ASIC

    Amount: $124,926.00

    The proposed 45 nm radiation hardened platform based structured ASIC architecture offers the performance and density expected of a custom ASIC with the low manufacturing cost associated with a structu ...

    SBIR Phase I 2012 National Aeronautics and Space Administration
  4. Conformal Load Bearing Antenna Structure

    Amount: $149,990.00

    ABSTRACT: American Semiconductor will develop and demonstrate structural integration of a conformal load bearing antenna structure (CLAS). Future aircraft will incorporate distributed electronics, s ...

    SBIR Phase I 2012 Department of Defense
  5. Next-Generation Detector and Imager Development

    Amount: $999,954.00

    Existing silicon on insulator (SOI) pixel detectors which integrate single gate transistors with substrate diodes are limited by two key problems. First, the SOI transistor performance is degraded by ...

    SBIR Phase II 2011 Department of Energy
  6. Ultra Low Power, Radiation Hardened, Reconfigurable Analog-to-Digital Converter

    Amount: $99,963.00

    The goal of this project is to develop an ultra low power (ULP), radiation hardened, reconfigurable analog-to-digital converter (ADC) in the 130nm Flexfet Independently Double Gated SOI CMOS process. ...

    SBIR Phase I 2011 Department of Defense
  7. High Performance, Ultra Low Power SPA-1 ASIC for Space Plug-and-Play Avionics

    Amount: $749,365.00

    ABSTRACT: The Space Plug-and-play Avionics (SPA) initiative is designed to improve the ability of the US military to respond to rapidly changing operational needs by creating, integrating, and launch ...

    SBIR Phase II 2011 Department of Defense
  8. Ultra Low Power, High Performance Microprocessor Core for Military and Space Applications

    Amount: $99,869.00

    For Phase I, an ultra low power, high performance microprocessor core using a combination of double-gated and independent double-gated FlexfetT SOI CMOS technology from American Semiconductor will be ...

    SBIR Phase I 2010 Air ForceDepartment of Defense
  9. Next-Generation Detector and Imager Development

    Amount: $99,971.00

    Improvements in silicon-on-insulator (SOI) technology have resulted in development of monolithic chip designs for radiation image sensors and particle detectors by facilitating the use of the handle s ...

    SBIR Phase I 2010 Department of Energy
  10. Direct Write via Digital Beam Processing for Rad-Hard Flexfet CMOS

    Amount: $99,917.00

    The is an effort to increase radiation hardness/survivability of microelectronics through innovation of production processes and capabilities by establishing an economically viable low-volume sub-65nm ...

    SBIR Phase I 2009 Missile Defense AgencyDepartment of Defense

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