Direct Write via Digital Beam Processing for Rad-Hard Flexfet CMOS

Award Information
Agency:
Department of Defense
Branch
Missile Defense Agency
Amount:
$99,917.00
Award Year:
2009
Program:
SBIR
Phase:
Phase I
Contract:
HQ0006-09-C-7134
Agency Tracking Number:
B083-023-0565
Solicitation Year:
2008
Solicitation Topic Code:
MDA08-023
Solicitation Number:
2008.3
Small Business Information
American Semiconductor, Inc.
3100 S. Vista Ave., Suite 230, Boise, ID, 83705
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
076338677
Principal Investigator:
Douglas Hackler
President & CEO
(208) 336-2773
doughackler@americansemi.com
Business Contact:
Lorelli Hackler
CFO
(208) 336-2773
lhackler@americansemi.com
Research Institution:
n/a
Abstract
The is an effort to increase radiation hardness/survivability of microelectronics through innovation of production processes and capabilities by establishing an economically viable low-volume sub-65nm rad-hard foundry CMOS capability based on Digital Beam Processing (DBP) technology. American Semiconductor (ASI) and Digibeam Corporation (DBC) propose a collaboration to evaluate sub-65nm radiation-hardened Flexfet™ CMOS realized in resistless, direct-write, DBP. This project will determine feasibility for CMOS integration of DBP as a supply solution for Ballistic Missile Defense System (BMDS) requirements. This SBIR includes both technical and economic analysis. DBP integration and sub-65nm Flexfet feasibility are evaluated using optical proximity test cells manufactured by integrating a DBP process step into a CMOS fabrication sequence. DBP will be applied to ASI’s existing design files, fabricated, and evaluated with ASI’s advanced metrology capability. DBP evaluation data will be used as input to sub-65nm Flexfet simulations. This project includes a scope typically beyond Phase I funding but that is feasible due to ASI’s unique low-volume foundry capability. Work includes: (1) Fabrication, simulation and modeling of DBP test cells, (2) DBP comparison to traditional photolithography, (3) Economic and technical evaluation including assessment of technical readiness (4) Determination of feasibility with cost model for radiation-hardened sub-65nm Flexfet DBP CMOS.

* information listed above is at the time of submission.

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