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High Speed Digitizer for Remote Sensing

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX15CP16C
Agency Tracking Number: 145484
Amount: $749,406.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: S1.02
Solicitation Number: N/A
Solicitation Year: 2014
Award Year: 2015
Award Start Date (Proposal Award Date): 2015-06-05
Award End Date (Contract End Date): 2018-02-04
Small Business Information
1616 E Main St Ste 221, Mesa, AZ, 85203-9074
DUNS: 000000000
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Esko Mikkola
 Principal Investigator
 (520) 647-4445
Business Contact
 Esko Mikkola
Title: Business Official
Phone: (520) 647-4445
Research Institution
This SBIR Phase II proposal requests support for Alphacore, Inc. to design and characterize a 24 Gsps (gigasamples per second), wide input bandwidth (40 GHz), 6-bit (5.0 effective number of bits, ENOB), low-power (700 mW), and low-cost analog-to-digital converter (ADC) for use in a wide range of NASA's microwave sensor remote sensing applications. The ADC does not employ time-interleaving and provides a very wide spur free input bandwidth making it more suitable to NASA's remote sensing missions and a variety of radio astronomy applications than any other ADC available. In addition, the ADC will be radiation hard (>300krad) and thus suitable for use on-board space missions. A key innovation in Alphacore's approach to the ADC design is that we have considered how the ADC will be used in a system; a custom designed digital back-end implements digital data de-multiplexing and signal conditioning to allow seamless integration with commercially available, high-end, field programmable gate arrays (FPGA) that are the main building blocks of modern scientific spectrometers and interferometers. Alphacore's ADC provides these improvements at much lower power and lower cost than existing commercial ADCs that use off-chip components to provide these features. Alphacore's design takes advantage of the latest low-power, high-speed digital CMOS processes, resulting in ADC power consumption that is less than 1/8 of the power consumption of competitor ADCs. The proposed ADC employs an innovative topology with high-bandwidth front-end sampling circuit combined with an interpolated flash-type ADC and encoder circuitry that simplifies FPGA interfacing. All the needed clock signals are generated from a low-cost 100MHz crystal clock reference with a low-jitter (<200fs), radiation-tolerant on-chip PLL.

* Information listed above is at the time of submission. *

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