LOW THRESHOLD MULTIPLE QUANTUM WELL LASER FOR HIGH DENSITY ELECTRONIC PACKING APPLICATIONS

Award Information
Agency:
Department of Defense
Branch
Defense Advanced Research Projects Agency
Amount:
$49,993.00
Award Year:
1989
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Award Id:
9442
Agency Tracking Number:
9442
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
2950 Ne 84th Ln, Blaine, MN, 55434
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Dr M Asif Khan
(612) 784-4995
Business Contact:
() -
Research Institute:
n/a
Abstract
OPTICAL INTERCONNECT TECHNOLOGY PROMISES TO PROVIDE SIGNIFICANT RELIEF FROM THE PINOUT PROBLEM, DECREASE IMPLEMENTATION COMPLEXITY, AND PROVIDE IMPROVEMENTS TO THE FLEXIBILITY AND REAL-TIME RECONFIGURATION FOR HIGH DENSITY ELECTRONIC PACKING APPLICATIONS SUCH AS VLSI/VHSIC. OPTICAL INTERCONNECT REQUIREMENTS, IN GENERAL, CAN BE DIVIDED INTO FOUR AREAS: DEVICES, ROUTING MECHANISMS, PACKING TECHNIQUES, AND ARCHITECTURE DEVELOPMENTS. IN PARTICULAR, DEVICES WHICH CAN TRANSFORM ELECTRICAL SIGNALS TO TOPICAL SIGNALS AND VICE VERSA (SEMICONDUCTOR DIODE LASERS, LIGHT EMITTING DIODES, DETECTORS) ARE REQUIRED TO IMPLEMENT OPTICAL INTERCONNECTS. LOW THRESHOLD HIGH SPEED LASERS BEYOND THE CURRENT STATE-OF-THE-ART ARE REQUIRED TO ADDRESS SPEED, AND LARGE FANOUT PROBLEMS. IN PHASE I OF THE PROPOSED EFFORT WE PROPOSE THE DEVELOPMENT OF A HIGH SPEED DIRECT CURRENT MODULATION MQW LASER BASED UPON OUR UNIQUE APPROACH OF REDUCING THE DEVICE CAPACITANCE BY USING SEMI-INSULATING SUBSTRATES AND ETCHING THE BOTTOM N + CONDUCTION LAYER FROM UNDER THE TOP CONTACT PAD. TO THE BEST OF OUR KNOWLEDGE, SUCH AN APPROACH HAS NEVER BEEN TRIED BEFORE. WE FEEL THIS DECREASE OF CAPACITANCE WILL RESULT IN AN INCREASE OF THE MAXIMUM RELAXATION OSCILLATION FREQUENCY. THE FIRST PHASE WILL CONSIST OF PERFORMING REQUIREMENTS AND DESIGN ANALYSIS, FABRICATING LASERS OF SI AND N + SUBSTRATES AND COMPARING THEIR RELAXATION OSCILLATION FREQUENCIES TO PROVE THE VALIDITY OF OUR TECHNICAL APPROACH. THE SECOND PHASE WILL BE AIMED AT DEVICE OPTIMIZATION, PACKAGING ISSUES, BUILDING AND TESTING A DEMO MODEL FOR DEMONSTRATING THE HIGH DENSITY ELECTRONIC PACKING APPLICATION.

* information listed above is at the time of submission.

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