Aries Design Automation, LLC

Basic Information

IL
Chicago, IL, 60618-3745

http://www.aries-da.com

Company Profile

n/a

Additional Details

Field Value
DUNS: 361627933
Hubzone Owned: N
Socially and Economically Disadvantaged: N
Woman Owned: N
Number of Employees: 5


  1. Scalable Parallel Algorithms for Formal Verification of Software

    Amount: $125,000.00

    We will develop an efficient Graphics Processing Unit (GPU) based parallel Binary Decision Diagram (BDD) software package, and will also combine it with our GPU-based parallel SAT solver that we are c ...

    SBIR Phase I 2013 National Aeronautics and Space Administration
  2. Formal Verification of Interactions of the RTOS, Memory System, and Application Programs at the PowerPC 750 Binary Code Level

    Amount: $125,000.00

    In the proposed project, we will formally verify the correctness of the interaction between a Real-Time Operating System (RTOS) and user processes under various operating scenarios, such as multitaski ...

    SBIR Phase I 2013 National Aeronautics and Space Administration
  3. Scalable Parallel Algorithms for Formal Verification of Software

    Amount: $125,000.00

    We will develop a prototype of a GPU-based parallel Binary Decision Diagram (BDD) software package. BDDs are a data structure that satisfies some simple restrictions, resulting in a unique representat ...

    SBIR Phase I 2012 National Aeronautics and Space Administration
  4. Using Automated Abstractions to Classify System States for Software Health Monitoring

    Amount: $90,000.00

    In most critical software systems, a state that is partially visible through values passed across interfaces contains information that could determine the health of the software system, and whether a ...

    SBIR Phase I 2011 National Institute of Standards and TechnologyDepartment of Commerce
  5. Reconfigurable VLIW Processor for Software Defined Radio

    Amount: $600,000.00

    We will implement an environment for design, formal verification, compilation of code, and performance and power evaluation of Systems on a Chip (SOCs) consisting of heterogeneous processor cores that ...

    SBIR Phase II 2011 National Aeronautics and Space Administration
  6. Reconfigurable VLIW Processor for Software Defined Radio

    Amount: $100,000.00

    We will design and formally verify a VLIW processor that is radiation-hardened, and where the VLIW instructions consist of predicated RISC instructions from the PowerPC 750 Instruction Set Architectur ...

    SBIR Phase I 2010 National Aeronautics and Space Administration
  7. An Efficient Parallel SAT Solver Exploiting Multi-Core Environments

    Amount: $600,000.00

    The hundreds of stream cores in the latest graphics processors (GPUs), and the possibility to execute non-graphics computations on them, open unprecedented levels of parallelism at a very low cost. In ...

    SBIR Phase II 2010 National Aeronautics and Space Administration
  8. Exploiting GPUs for Scalable Network Intrusion Detection

    Amount: $100,000.00

    In this proposed SBIR Phase I project, we will develop a proto

    SBIR Phase I 2010 Department of Energy
  9. SBIR Phase I: Automatic Formal Verification of Chip-Multi-Threaded Multicore Processors

    Amount: $150,000.00

    This Small Business Innovation Research (SBIR) Phase I project will result in an efficient and scalable method for design and formal verification of Chip-Multi-Threaded multicore processors, where the ...

    SBIR Phase I 2010 National Science Foundation
  10. An Efficient Parallel SAT Solver Exploiting Multi-Core Environments

    Amount: $100,000.00

    The hundreds of stream cores in the latest graphics processors (GPUs), and the possibility to execute non-graphics computations on them, open unprecedented levels of parallelism at a very low cost. We ...

    SBIR Phase I 2009 National Aeronautics and Space Administration

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