Aries Design Automation, LLC

Company Information
Address IL
Chicago, IL, 60618-3745


DUNS: 361627933

# of Employees: 5

Ownership Information

HUBZone Owned: N

Socially and Economically Disadvantaged: N

Woman Owned: N

Award Charts

Award Listing

  1. Scalable Parallel Algorithms for Formal Verification of Software

    Amount: $125,000.00

    We will develop an efficient Graphics Processing Unit (GPU) based parallel Binary Decision Diagram (BDD) software package, and will also combine it with our GPU-based parallel SAT solver that we are c ...

    SBIRPhase I2013National Aeronautics and Space Administration
  2. Formal Verification of Interactions of the RTOS, Memory System, and Application Programs at the PowerPC 750 Binary Code Level

    Amount: $125,000.00

    In the proposed project, we will formally verify the correctness of the interaction between a Real-Time Operating System (RTOS) and user processes under various operating scenarios, such as multitaski ...

    SBIRPhase I2013National Aeronautics and Space Administration
  3. Scalable Parallel Algorithms for Formal Verification of Software

    Amount: $125,000.00

    We will develop a prototype of a GPU-based parallel Binary Decision Diagram (BDD) software package. BDDs are a data structure that satisfies some simple restrictions, resulting in a unique representat ...

    SBIRPhase I2012National Aeronautics and Space Administration
  4. Using Automated Abstractions to Classify System States for Software Health Monitoring

    Amount: $90,000.00

    In most critical software systems, a state that is partially visible through values passed across interfaces contains information that could determine the health of the software system, and whether a ...

    SBIRPhase I2011Department of Commerce National Institute of Standards and Technology
  5. Reconfigurable VLIW Processor for Software Defined Radio

    Amount: $600,000.00

    We will implement an environment for design, formal verification, compilation of code, and performance and power evaluation of Systems on a Chip (SOCs) consisting of heterogeneous processor cores that ...

    SBIRPhase II2011National Aeronautics and Space Administration
  6. Reconfigurable VLIW Processor for Software Defined Radio

    Amount: $100,000.00

    We will design and formally verify a VLIW processor that is radiation-hardened, and where the VLIW instructions consist of predicated RISC instructions from the PowerPC 750 Instruction Set Architectur ...

    SBIRPhase I2010National Aeronautics and Space Administration
  7. An Efficient Parallel SAT Solver Exploiting Multi-Core Environments

    Amount: $600,000.00

    The hundreds of stream cores in the latest graphics processors (GPUs), and the possibility to execute non-graphics computations on them, open unprecedented levels of parallelism at a very low cost. In ...

    SBIRPhase II2010National Aeronautics and Space Administration
  8. SBIR Phase I: Automatic Formal Verification of Chip-Multi-Threaded Multicore Processors

    Amount: $150,000.00

    This Small Business Innovation Research (SBIR) Phase I project will result in an efficient and scalable method for design and formal verification of Chip-Multi-Threaded multicore processors, where the ...

    SBIRPhase I2010National Science Foundation
  9. Exploiting GPUs for Scalable Network Intrusion Detection

    Amount: $100,000.00

    In this proposed SBIR Phase I project, we will develop a proto

    SBIRPhase I2010Department of Energy
  10. Efficient Techniques for Formal Verification of PowerPC 750 Executables

    Amount: $600,000.00

    We will develop an efficient tool for formal verification of PowerPC 750 executables. The PowerPC 750 architecture is used in the radiation-hardened RAD750 flight-control computers that are utilized i ...

    SBIRPhase II2009National Aeronautics and Space Administration

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