Efficient Techniques for Formal Verification of PowerPC 750 Executables

Award Information
Agency:
National Aeronautics and Space Administration
Amount:
$600,000.00
Program:
SBIR
Contract:
NNX09CA19C
Solitcitation Year:
2007
Solicitation Number:
N/A
Branch:
N/A
Award Year:
2009
Phase:
Phase II
Agency Tracking Number:
075477
Solicitation Topic Code:
X1.02
Small Business Information
Aries Design Automation, LLC
6157 N Sheridan Road, Suite 16M, Chicago, IL, 60660-5818
Hubzone Owned:
N
Woman Owned:
N
Socially and Economically Disadvantaged:
N
Duns:
361627933
Principal Investigator
 Miroslav Velev
 Principal Investigator
 (773) 856-6633
 miroslav.velev@aries-da.com
Business Contact
 Miroslav Velev
Title: Business Official
Phone: (773) 856-6633
Email: miroslav.velev@aries-da.com
Research Institution
N/A
Abstract
We will develop an efficient tool for formal verification of PowerPC 750 executables. The PowerPC 750 architecture is used in the radiation-hardened RAD750 flight-control computers that are utilized in many space missions. The resulting tool will be capable of formally checking: 1) the equivalence of two instruction sequences; and 2) properties of a given instruction sequence. The tool will automatically introduce symbolic state for state variables that are not initialized and for external inputs. We bring a tremendous expertise in formal verification of complex microprocessors, formal definition of instruction semantics, and efficient translation of formulas from formal verification to Boolean Satisfiability (SAT). We will also produce formally verified definitions of the PowerPC 750 instructions used in the project, expressed in synthesizable Verilog; these definitions could be utilized for formal verification and testing of PowerPC 750 compatible processors, for FPGA-based emulation of PowerPC 750 executables, as well as in other formal verification tools to be implemented in the future.

* information listed above is at the time of submission.

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