Processing Signals In High Density Electromagnetic Environments

Award Information
Agency:
Department of Defense
Branch
Navy
Amount:
$449,983.00
Award Year:
2010
Program:
SBIR
Phase:
Phase II
Contract:
N00024-10-C-4137
Award Id:
87800
Agency Tracking Number:
N082-165-0004
Solicitation Year:
n/a
Solicitation Topic Code:
NAVY 08-165
Solicitation Number:
n/a
Small Business Information
111 Dart Circle, Rome, NY, 13441
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
153924188
Principal Investigator:
Brian Bush
Research Engineer
(315) 339-4800
bbush@ras.com
Business Contact:
Stan Hall
Vice President of Operati
(315) 339-4800
shall@ras.com
Research Institution:
n/a
Abstract
High level signals from on-board emitters result in large interference and dynamic range under which low-level signals must be detected while maintaining spectral coverage and minimizing temporal blanking. In Phase I, RAS showed the efficacy of a multi-pronged approach consisting of adaptive RF cancellation (CARFIS) in the RF front-end to remove strong interference and mitigate component saturation in conjunction with time-frequency excision (TFEX) and pulse interference detection and characterization (IDEC). signal processing techniques to further reduce large signals and detect and characterize remaining signals. These techniques can be incorporated with RF selectable filtering, attenuation, or limiting to further enhance the interference mitigation. In Phase II, hardware prototypes with VHDL and NDI low cost hardware elements will be developed and tested. Existing FPGA designs for real-time parameter measurements including features, and techniques for intentional modulation on pulse characterization will be leveraged for time-based IDEC processing. The capability to utilize knowledge of own-ship radar transmission parameters and timing will be incorporated. System architecture and MATLABTM algorithms will be refined and characterized in Phase II and VHDL cores designed. An IDEC prototype with CARFIS models will be developed using open architecture COTS and NDI hardware compatible with the SEWIP Block II architecture.

* information listed above is at the time of submission.

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