Processing Signals In High Density Electromagnetic Environments

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N00024-10-C-4137
Agency Tracking Number: N082-165-0004
Amount: $449,983.00
Phase: Phase II
Program: SBIR
Awards Year: 2010
Solicitation Year: 2008
Solicitation Topic Code: N08-165
Solicitation Number: 2008.2
Small Business Information
111 Dart Circle, Rome, NY, 13441
DUNS: 153924188
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Brian Bush
 Research Engineer
 (315) 339-4800
Business Contact
 Stan Hall
Title: Vice President of Operati
Phone: (315) 339-4800
Research Institution
High level signals from on-board emitters result in large interference and dynamic range under which low-level signals must be detected while maintaining spectral coverage and minimizing temporal blanking. In Phase I, RAS showed the efficacy of a multi-pronged approach consisting of adaptive RF cancellation (CARFIS) in the RF front-end to remove strong interference and mitigate component saturation in conjunction with time-frequency excision (TFEX) and pulse interference detection and characterization (IDEC). signal processing techniques to further reduce large signals and detect and characterize remaining signals. These techniques can be incorporated with RF selectable filtering, attenuation, or limiting to further enhance the interference mitigation. In Phase II, hardware prototypes with VHDL and NDI low cost hardware elements will be developed and tested. Existing FPGA designs for real-time parameter measurements including features, and techniques for intentional modulation on pulse characterization will be leveraged for time-based IDEC processing. The capability to utilize knowledge of own-ship radar transmission parameters and timing will be incorporated. System architecture and MATLABTM algorithms will be refined and characterized in Phase II and VHDL cores designed. An IDEC prototype with CARFIS models will be developed using open architecture COTS and NDI hardware compatible with the SEWIP Block II architecture.

* Information listed above is at the time of submission. *

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