Device-Quality, Low-Defect Hybrid SiC Wafers
Department of Defense
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2500 Central Ave., Boulder, CO, 80301
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AbstractResearchers at Astralux, Inc. in collaboration with PowerSicel, Inc and the University of Colorado at Boulder propose to develop hybrid SiC wafers using a novel technique. Specifically, our goal is to commercialize low-defect, epi-ready 3-inch and 4-inchSiC wafers. We will develop conducting substrates for both near-dc high voltage/power and optoelectronics, as well as semi-insulating wafers for RF power devices. Our hybrid SiC wafers are complementary to the existing bulk SiC wafers, and our value addedis to reduce stress, decrease defects, increase the production volume and significantly reduce the cost of larger-area substrates. During Phase I, researchers at Astralux demonstrated 35 mm hybrid SiC wafers with an epitaxial GaN growth demonstration. AllPhase I milestones were reached, the goals accomplished and we are now ready for prototype development in Phase II. In Phase II, the quality of the hybrid wafers will be validated through a SiC RF device demonstration.
* information listed above is at the time of submission.